49 lines
1.9 KiB
Plaintext
49 lines
1.9 KiB
Plaintext
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#
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# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
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#
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# In this HDL repository, there are many different and unique modules, consisting
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# of various HDL (Verilog or VHDL) components. The individual modules are
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# developed independently, and may be accompanied by separate and unique license
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# terms.
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#
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# The user should read each of these license terms, and understand the
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# freedoms and responsibilities that he or she has by using this source/core.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE.
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#
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# Redistribution and use of source or resulting binaries, with or without modification
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# of this file, are permitted under one of the following two license terms:
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#
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# 1. The GNU General Public License version 2 as published by the
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# Free Software Foundation, which can be found in the top level directory
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# of this repository (LICENSE_GPL2), and also online at:
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# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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#
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# OR
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#
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# 2. An ADI specific BSD license, which can be found in the top level directory
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# of this repository (LICENSE_ADIBSD), and also on-line at:
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# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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# This will allow to generate bit files and not release the source code,
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# as long as it attaches to an ADI device.
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#
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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# Maximum lane rate of 14.2 Gbps however the dacfifo does not meet the 355 MHz requirement, reducing it to 333MHz
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create_clock -period "3 ns" -name tx_ref_clk [get_ports {tx_ref_clk}]
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# Asynchronous GPIOs
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foreach async_input {gpio_bd_i[*]} {
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set_false_path -from [get_ports $async_input]
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}
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foreach async_output {gpio_bd_o[*] txen_0 txen_1 spi_en_n} {
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set_false_path -to [get_ports $async_output]
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}
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derive_pll_clocks
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derive_clock_uncertainty
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