261 lines
9.8 KiB
Coq
261 lines
9.8 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_ad5766_sequencer #(
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parameter SEQ_ID = 0)(
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input sequence_clk,
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input sequence_rst,
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input sequence_req,
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output reg sequence_valid,
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output reg [ 7:0] sequence_data,
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output reg [31:0] up_rdata,
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output reg up_rack);
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// registers
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reg [ 7:0] up_sequencer[15:0];
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reg [ 3:0] up_endof_seq = 4'b0;
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reg up_xfer_req = 1'b0;
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reg [ 3:0] sequence_counter = 0;
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// internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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wire [ 7:0] sequencer[15:0];
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wire [ 3:0] end_of_sequence;
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integer i;
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// sequence counter
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always @(posedge sequence_clk) begin
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if (sequence_rst) begin
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sequence_counter <= 4'b0;
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end else if (sequence_req) begin
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sequence_counter <= (sequence_counter == end_of_sequence) ? 0 : sequence_counter + 1;
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end
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end
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// sequence output mux
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always @(posedge sequence_clk) begin
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if (sequence_rst) begin
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sequence_data <= 16'b0;
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end
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else if (sequence_req) begin
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sequence_data <= sequencer[sequence_counter];
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end
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sequence_valid <= sequence_req;
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end
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// decode block select
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assign up_wreq_s = (up_waddr[13:8] == SEQ_ID) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:8] == SEQ_ID) ? up_rreq : 1'b0;
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// processor write interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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for (i=0; i<16; i=i+1) begin
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up_sequencer[i] <= 8'b0;
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end
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up_endof_seq <= 4'b0;
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up_wack <= 1'b0;
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end else begin
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h40)) begin
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up_sequencer[0] <= up_wdata[7:0];
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up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h41)) begin
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up_sequencer[1] <= up_wdata[7:0];
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up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h42)) begin
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up_sequencer[2] <= up_wdata[7:0];
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up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h43)) begin
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up_sequencer[3] <= up_wdata[7:0];
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up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h44)) begin
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up_sequencer[4] <= up_wdata[7:0];
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up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h45)) begin
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up_sequencer[5] <= up_wdata[7:0];
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up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h46)) begin
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up_sequencer[6] <= up_wdata[7:0];
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up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h47)) begin
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up_sequencer[7] <= up_wdata[7:0];
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up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h48)) begin
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up_sequencer[8] <= up_wdata[7:0];
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up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h49)) begin
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up_sequencer[9] <= up_wdata[7:0];
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up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4a)) begin
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up_sequencer[10] <= up_wdata[7:0];
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up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4b)) begin
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up_sequencer[11] <= up_wdata[7:0];
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up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4c)) begin
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up_sequencer[12] <= up_wdata[7:0];
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up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4d)) begin
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up_sequencer[13] <= up_wdata[7:0];
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up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4e)) begin
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up_sequencer[14] <= up_wdata[7:0];
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up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4f)) begin
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up_sequencer[15] <= up_wdata[7:0];
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up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr[7:0])
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8'h40 : up_rdata <= {24'b0, up_sequencer[0]};
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8'h41 : up_rdata <= {24'b0, up_sequencer[1]};
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8'h42 : up_rdata <= {24'b0, up_sequencer[2]};
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8'h43 : up_rdata <= {24'b0, up_sequencer[3]};
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8'h44 : up_rdata <= {24'b0, up_sequencer[4]};
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8'h45 : up_rdata <= {24'b0, up_sequencer[5]};
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8'h46 : up_rdata <= {24'b0, up_sequencer[6]};
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8'h47 : up_rdata <= {24'b0, up_sequencer[7]};
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8'h48 : up_rdata <= {24'b0, up_sequencer[8]};
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8'h49 : up_rdata <= {24'b0, up_sequencer[9]};
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8'h4a : up_rdata <= {24'b0, up_sequencer[10]};
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8'h4b : up_rdata <= {24'b0, up_sequencer[11]};
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8'h4c : up_rdata <= {24'b0, up_sequencer[12]};
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8'h4d : up_rdata <= {24'b0, up_sequencer[13]};
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8'h4e : up_rdata <= {24'b0, up_sequencer[14]};
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8'h4f : up_rdata <= {24'b0, up_sequencer[15]};
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8'h60 : up_rdata <= {27'b0, up_xfer_req, up_endof_seq};
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endcase
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end else begin
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up_rdata <= 32'b0;
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end
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end
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end
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// CDC
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up_xfer_cntrl #(.DATA_WIDTH(132)) i_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_cntrl ({up_endof_seq,
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up_sequencer[0],
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up_sequencer[1],
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up_sequencer[2],
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up_sequencer[3],
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up_sequencer[4],
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up_sequencer[5],
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up_sequencer[6],
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up_sequencer[7],
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up_sequencer[8],
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up_sequencer[9],
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up_sequencer[10],
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up_sequencer[11],
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up_sequencer[12],
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up_sequencer[13],
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up_sequencer[14],
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up_sequencer[15]}),
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.up_xfer_done (up_cntrl_xfer_done),
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.d_rst (sequence_rst),
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.d_clk (sequence_clk),
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.d_data_cntrl ({end_of_sequence,
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sequencer[0],
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sequencer[1],
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sequencer[2],
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sequencer[3],
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sequencer[4],
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sequencer[5],
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sequencer[6],
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sequencer[7],
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sequencer[8],
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sequencer[9],
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sequencer[10],
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sequencer[11],
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sequencer[12],
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sequencer[13],
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sequencer[14],
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sequencer[15]}));
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endmodule
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