2017-02-28 18:30:50 +00:00
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2017-05-12 17:25:17 +00:00
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package require qsys
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2017-02-28 18:30:50 +00:00
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_alt.tcl
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ad_ip_create util_dacfifo {UTIL DAC FIFO Interface}
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ad_ip_files util_dacfifo [list\
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$ad_hdl_dir/library/common/ad_mem.v \
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2017-10-05 11:20:54 +00:00
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$ad_hdl_dir/library/common/ad_b2g.v \
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$ad_hdl_dir/library/common/ad_g2b.v \
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2017-02-28 18:30:50 +00:00
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util_dacfifo.v \
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util_dacfifo_constr.sdc]
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# parameters
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ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
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ad_ip_parameter ADDRESS_WIDTH INTEGER 6
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ad_ip_parameter DATA_WIDTH INTEGER 128
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# interfaces
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ad_alt_intf clock dma_clk input 1 clk
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ad_alt_intf reset dma_rst input 1 if_dma_clk
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ad_alt_intf signal dma_valid input 1 valid
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ad_alt_intf signal dma_data input DATA_WIDTH data
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ad_alt_intf signal dma_ready output 1 ready
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ad_alt_intf signal dma_xfer_req input 1 xfer_req
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ad_alt_intf signal dma_xfer_last input 1 last
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ad_alt_intf clock dac_clk input 1
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2017-03-03 16:43:36 +00:00
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ad_alt_intf reset dac_rst input 1 if_dac_clk
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2017-02-28 18:30:50 +00:00
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ad_alt_intf signal dac_valid input 1 valid
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ad_alt_intf signal dac_data output DATA_WIDTH data
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ad_alt_intf signal dac_xfer_out output 1 xfer_req
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2017-03-03 16:43:36 +00:00
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ad_alt_intf signal dac_dunf output 1 unf
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2017-02-28 18:30:50 +00:00
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ad_alt_intf signal bypass input 1 bypass
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