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pluto_hdl_adi/library/intel/avl_dacfifo/avl_dacfifo_constr.sdc

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avl_dacfifo: Initial commit
2017-04-21 10:26:37 +00:00
# CDC paths
avl_dacfifo: Refactor the fifo + Build both the read and write logic around an FSM + Consistent naming of registers and wires + Add support for burst lenghts higher than one, current burst lenght is 64 + Fix all the bugs, and make it work (first bring up with adrv9371x/a10soc)
2017-10-17 12:10:06 +00:00
set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|dac_mem_raddr_g*] \
-to [get_registers *avl_dacfifo_rd:i_rd|avl_mem_raddr_m1*]
set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|avl_mem_waddr_g*] \
-to [get_registers *avl_dacfifo_rd:i_rd|dac_mem_waddr_m1*]
set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|avl_xfer_req_out*] \
-to [get_registers *avl_dacfifo_rd:i_rd|dac_avl_xfer_req_m1*]
set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|avl_mem_laddr_toggle*] \
-to [get_registers *avl_dacfifo_rd:i_rd|dac_mem_laddr_toggle_m[0]]
set_false_path -to [get_registers *avl_dacfifo_rd:i_rd|dac_mem_laddr*]
set_false_path -to [get_registers *avl_dacfifo_rd:i_rd|dac_dma_last_beats_m1*]
set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|avl_xfer_req_lp*] \
-to [get_registers *avl_dacfifo_wr:i_wr|dma_xfer_req_lp_m1*]
set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|avl_xfer_req_out*] \
-to [get_registers *avl_dacfifo_wr:i_wr|dma_avl_xfer_req_out_m1*]
set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|avl_mem_raddr_g*] \
-to [get_registers *avl_dacfifo_wr:i_wr|dma_mem_raddr_m1*]
set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_xfer_req*] \
-to [get_registers *avl_dacfifo_wr:i_wr|avl_dma_xfer_req_m1*]
set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_mem_waddr_g*] \
-to [get_registers *avl_dacfifo_wr:i_wr|avl_mem_waddr_m1*]
set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_last_beats*] \
-to [get_registers *avl_dacfifo_wr:i_wr|avl_dma_last_beats_m1*]
set_false_path -from [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dac_mem_raddr_g*] \
-to [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dma_mem_raddr_m1*]
set_false_path -from [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dma_mem_waddr_g*] \
-to [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dac_mem_waddr_m1*]
set_false_path -to [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dac_xfer_out_m1*]
avl_dacfifo: Update constraints
2017-04-21 14:25:23 +00:00
avl_dacfifo: Update constraints
2017-05-23 11:16:10 +00:00
set_false_path -to [get_registers *avl_dacfifo:*avl_dma_xfer_req_m1*]
set_false_path -to [get_registers *avl_dacfifo:*dac_xfer_out_m1*]
avl_dacfifo: Update constarint file
2017-04-25 09:03:46 +00:00
set_false_path -to [get_registers *avl_dacfifo:*bypass_m1*]
avl_dacfifo: Initial commit
2017-04-21 10:26:37 +00:00
avl_dacfifo: add missing constraint
2019-05-14 13:18:47 +00:00
set_false_path -to [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dma_rst_m1*]