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pluto_hdl_adi/library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl

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axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
# ip
axi_dacfifo: Move IP to library/xilinx
2016-09-15 08:38:16 +00:00
source ../../scripts/adi_env.tcl
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_dacfifo
adi_ip_files axi_dacfifo [list \
axi_dacfifo: Add gray coder/decoder module Use gray coder/decoder modules, instead of functions. This way it can be used paramterized data width on the coders/decoders.
2017-07-06 08:47:26 +00:00
"$ad_hdl_dir/library/common/ad_g2b.v" \
"$ad_hdl_dir/library/common/ad_b2g.v" \
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
axi_dacfifo: Major update and redesign Redesign the axi_dacfifo, to increase the supported datarates. Major modifications: + The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac was deprecated. + Both the AXI write and AXI read transaction are controlled by two FSM, to increase redability of the code. + Support all the possible burst lengths [0..225], handles the last fractional burst on both sides correctly. + Common reset architecture throughout the design, all the internal registers and memories are reset on the posedge of dma_xfer_req + Delete all Altera related sources, for Altera projects avl_dacfifo should be used. WIP: foobar [WIP]axi_dacfifo: Update axi_dacfifo: Few minor updates, almost working state
2017-08-04 09:19:12 +00:00
"$ad_hdl_dir/library/common/ad_mem.v" \
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
axi_dacfifo: Move the axi_dac_fifo_bypass module to util_dac_fifo_bypass
2017-04-21 10:23:03 +00:00
"$ad_hdl_dir/library/common/util_dacfifo_bypass.v" \
library/axi_dacfifo: Update the bypass logic The bypass logic is located between the AXI read controller and the DAC CDC fifo. When the bypass is enabled the DMAC destination interface must be clocked with the PL_DDR controller's ui_clk. This way it can easily switch between the AXI read's stream and DMAC's stream interface.
2016-06-22 09:24:54 +00:00
"axi_dacfifo_constr.xdc" \
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
"axi_dacfifo_wr.v" \
"axi_dacfifo_rd.v" \
axi_dacfifo: Major update and redesign Redesign the axi_dacfifo, to increase the supported datarates. Major modifications: + The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac was deprecated. + Both the AXI write and AXI read transaction are controlled by two FSM, to increase redability of the code. + Support all the possible burst lengths [0..225], handles the last fractional burst on both sides correctly. + Common reset architecture throughout the design, all the internal registers and memories are reset on the posedge of dma_xfer_req + Delete all Altera related sources, for Altera projects avl_dacfifo should be used. WIP: foobar [WIP]axi_dacfifo: Update axi_dacfifo: Few minor updates, almost working state
2017-08-04 09:19:12 +00:00
"axi_dacfifo_address_buffer.v" \
library/axi_dacfifo: Update the bypass logic The bypass logic is located between the AXI read controller and the DAC CDC fifo. When the bypass is enabled the DMAC destination interface must be clocked with the PL_DDR controller's ui_clk. This way it can easily switch between the AXI read's stream and DMAC's stream interface.
2016-06-22 09:24:54 +00:00
"axi_dacfifo.v"]
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
adi_ip_properties_lite axi_dacfifo
dacfifo- axi address map fixes
2016-09-27 18:48:23 +00:00
ipx::infer_bus_interface {\
axi_awvalid \
axi_awid \
axi_awburst \
axi_awlock \
axi_awcache \
axi_awprot \
axi_awqos \
axi_awlen \
axi_awsize \
axi_awaddr \
axi_awready \
axi_wvalid \
axi_wdata \
axi_wstrb \
axi_wlast \
axi_wready \
axi_bvalid \
axi_bid \
axi_bresp \
axi_bready \
axi_arvalid \
axi_arid \
axi_arburst \
axi_arlock \
axi_arcache \
axi_arprot \
axi_arqos \
axi_arlen \
axi_arsize \
axi_araddr \
axi_arready \
axi_rvalid \
axi_rid \
axi_rresp \
axi_rlast \
axi_rdata \
axi_rready} \
xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
-of_objects [ipx::current_core]]
set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
-of_objects [ipx::get_bus_interfaces axi_clk \
-of_objects [ipx::current_core]]]
ipx::add_address_space axi [ipx::current_core]
set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \
-of_objects [ipx::current_core]]
set_property range 4294967296 [ipx::get_address_spaces axi \
-of_objects [ipx::current_core]]
set_property width 512 [ipx::get_address_spaces axi \
-of_objects [ipx::current_core]]
axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 08:28:33 +00:00
ipx::save_core [ipx::current_core]