pluto_hdl_adi/library/axi_dmac/response_handler.v

// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
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//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
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//
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//      This will allow to generate bit files and not release the source code,
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//
// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module dmac_response_handler #(

  parameter ID_WIDTH = 3)(

  input clk,
  input resetn,

  input bvalid,
  output bready,
  input [1:0] bresp,

  output reg [ID_WIDTH-1:0] id,
  input [ID_WIDTH-1:0] request_id,

  input enable,
  output reg enabled,

  input eot,

  output resp_valid,
  input resp_ready,
  output resp_eot,
  output [1:0] resp_resp
);

`include "resp.vh"
`include "inc_id.vh"

assign resp_resp = bresp;
assign resp_eot = eot;

wire active = id != request_id;

assign bready = active && resp_ready;
assign resp_valid = active && bvalid;

// We have to wait for all responses before we can disable the response handler
always @(posedge clk) begin
  if (resetn == 1'b0) begin
    enabled <= 1'b0;
  end else if (enable == 1'b1) begin
      enabled <= 1'b1;
  end else if (request_id == id) begin
      enabled <= 1'b0;
  end
end

always @(posedge clk) begin
  if (resetn == 1'b0) begin
    id <= 'h0;
  end else if (bready == 1'b1 && bvalid == 1'b1) begin
    id <= inc_id(id);
  end
end

endmodule