pluto_hdl_adi/library/common/ad_dds.v

// ***************************************************************************
// ***************************************************************************
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// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module ad_dds (

  // interface

  clk,
  dds_format,
  dds_phase_0,
  dds_scale_0,
  dds_phase_1,
  dds_scale_1,
  dds_data);

  // interface

  input           clk;
  input           dds_format;
  input   [15:0]  dds_phase_0;
  input   [15:0]  dds_scale_0;
  input   [15:0]  dds_phase_1;
  input   [15:0]  dds_scale_1;
  output  [15:0]  dds_data;

  // internal registers

  reg     [15:0]  dds_data_int = 'd0;
  reg     [15:0]  dds_data = 'd0;

  // internal signals

  wire    [15:0]  dds_data_0_s;
  wire    [15:0]  dds_data_1_s;

  // dds channel output

  always @(posedge clk) begin
    dds_data_int <= dds_data_0_s + dds_data_1_s;
    dds_data[15:15] <= dds_data_int[15] ^ dds_format;
    dds_data[14: 0] <= dds_data_int[14:0];
  end

  // dds-1

  ad_dds_1 i_dds_1_0 (
    .clk (clk),
    .angle (dds_phase_0),
    .scale (dds_scale_0),
    .dds_data (dds_data_0_s));

  // dds-2

  ad_dds_1 i_dds_1_1 (
    .clk (clk),
    .angle (dds_phase_1),
    .scale (dds_scale_1),
    .dds_data (dds_data_1_s));

endmodule

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