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pluto_hdl_adi/library/jesd204/interfaces/Makefile

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Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
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####################################################################################
M_DEPS := interfaces_ip.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_ip.tcl
M_VIVADO := vivado -mode batch -source
XML_FLIST := jesd204_tx_cfg.xml
XML_FLIST += jesd204_tx_cfg_rtl.xml
XML_FLIST += jesd204_tx_ilas_config.xml
XML_FLIST += jesd204_tx_ilas_config_rtl.xml
XML_FLIST += jesd204_tx_status.xml
XML_FLIST += jesd204_tx_status_rtl.xml
XML_FLIST += jesd204_tx_event.xml
XML_FLIST += jesd204_tx_event_rtl.xml
XML_FLIST += jesd204_tx_ctrl.xml
XML_FLIST += jesd204_tx_ctrl_rtl.xml
XML_FLIST += jesd204_rx_cfg.xml
XML_FLIST += jesd204_rx_cfg_rtl.xml
XML_FLIST += jesd204_rx_status.xml
XML_FLIST += jesd204_rx_status_rtl.xml
XML_FLIST += jesd204_rx_ilas_config.xml
XML_FLIST += jesd204_rx_ilas_config_rtl.xml
XML_FLIST += jesd204_rx_event.xml
XML_FLIST += jesd204_rx_event_rtl.xml
M_FLIST := *.log
M_FLIST += *.jou
M_FLIST += $(XML_FLIST)
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
.PHONY: all xilinx clean clean-all
all: xilinx
xilinx: $(XML_FLIST)
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
%.xml: $(M_DEPS)
$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
####################################################################################
####################################################################################