72 lines
1.6 KiB
Coq
72 lines
1.6 KiB
Coq
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`timescale 1ns/100ps
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module ad_mux_tb;
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parameter VCD_FILE = "ad_mux_tb.vcd";
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parameter CH_W = 16; // Width of input channel
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parameter CH_CNT = 64; // Number of input channels
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parameter REQ_MUX_SZ = 8; // Size of mux which acts as a building block
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parameter EN_REG = 1; // Enable register at output of each mux
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localparam MUX_SZ = CH_CNT < REQ_MUX_SZ ? CH_CNT : REQ_MUX_SZ;
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localparam NUM_STAGES = $clog2(CH_CNT) / $clog2(MUX_SZ);
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localparam DW = CH_W*CH_CNT;
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`include "tb_base.v"
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reg [CH_W*CH_CNT-1:0] data_in = 'h0;
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reg [$clog2(CH_CNT)-1:0] ch_sel = 'h0;
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wire [CH_W-1:0] data_out;
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ad_mux #(
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.CH_W(CH_W),
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.CH_CNT(CH_CNT),
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.REQ_MUX_SZ(REQ_MUX_SZ),
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.EN_REG(EN_REG)
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) DUT (
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.clk(clk),
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.data_in(data_in),
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.ch_sel(ch_sel),
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.data_out(data_out)
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);
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wire [CH_W-1:0] ref_data;
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generate
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if (EN_REG) begin
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integer ii;
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reg [CH_W*CH_CNT-1:0] mux_pln [1:NUM_STAGES];
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always @(posedge clk) begin
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mux_pln[1] <= data_in >> ch_sel*CH_W;
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for (ii=2; ii<=NUM_STAGES; ii=ii+1) begin
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mux_pln[ii] <= mux_pln[ii-1];
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end
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end
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assign ref_data = mux_pln[NUM_STAGES];
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end else begin
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assign ref_data = data_in >> ch_sel*CH_W;
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end
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endgenerate
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integer i;
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initial begin
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for (i=0; i<CH_W*CH_CNT/8; i=i+1) begin
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data_in[i*8+:8] = i[7:0];
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end
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for (i=0; i<CH_CNT; i=i+1) begin
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@(posedge clk);
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ch_sel <= ch_sel + 1;
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end
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end
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wire mismatch;
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assign mismatch = ref_data !== data_out;
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always @(posedge clk) begin
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if (mismatch) begin
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failed <= 1'b1;
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end
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end
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endmodule
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