pluto_hdl_adi/library/util_extract/util_extract_ip.tcl

# ip

source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl

adi_ip_create util_extract
adi_ip_files util_extract [list \
  "util_extract.v" ]

adi_ip_properties_lite util_extract

set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_extract} [ipx::current_core]

ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

ipx::save_core [ipx::current_core]
util_extract: Initial commit 2017-01-31 14:26:05 +00:00			`# ip`

scripts: Merge adi_env.tcl into a single file Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips 2022-07-12 11:06:15 +00:00			`source ../../scripts/adi_env.tcl`
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2018-08-14 09:59:39 +00:00			`source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl`
util_extract: Initial commit 2017-01-31 14:26:05 +00:00
			`adi_ip_create util_extract`
			`adi_ip_files util_extract [list \`
			`"util_extract.v" ]`

			`adi_ip_properties_lite util_extract`

library: Add link to wiki for IPs 2021-10-20 15:08:35 +00:00			`set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_extract} [ipx::current_core]`

axi_*: Infer clock and reset signals of an IP A clock sink must be connected to clock source, and a reset sink to reset source, otherwise the tool will throw a synthesis warning. By properly inferring all the reset and clock signals of an IP, we can get rid of unwanted warning messages. The following IPs tcl script was updated: - axi_ad9434 - axi_hdmi_tx - util_cpack - util_adxcvr - axi_ad6676 - axi_ad9625 - axi_ad9379 - axi_ad9265 - util_tdd_sync - util_rfifo - util_wfifo - axi_ad9361 - axi_ad9467 - util_upack - axi_dacfifo - axi_ad9152 - axi_ad9680 - util_clkdiv - axi_ad9122 - axi_ad9684 - axi_mc_speed - axi_mc_current_monitor - axi_mc_controller - util_gmii_to_rgmii - util_adxcvr - axi_ad9379 - axi_hdmi - library - axi_fmcadc5_sync - util_adcfifo - util_mfifo - axi_jesd204_rx - axi_jesd204_tx - axi_ad9361 - axi_adxcvr_ip 2018-02-15 08:41:14 +00:00			`ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]`

util_extract: Initial commit 2017-01-31 14:26:05 +00:00			`ipx::save_core [ipx::current_core]`