2015-06-26 09:04:19 +00:00
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// ***************************************************************************
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// ***************************************************************************
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2017-05-17 08:44:52 +00:00
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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2015-06-26 09:04:19 +00:00
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//
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2017-05-31 15:15:24 +00:00
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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2017-05-29 06:55:41 +00:00
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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2015-06-26 09:04:19 +00:00
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//
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2017-05-29 06:55:41 +00:00
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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2015-06-26 09:04:19 +00:00
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//
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2017-05-17 08:44:52 +00:00
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// 1. The GNU General Public License version 2 as published by the
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2017-05-31 15:15:24 +00:00
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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2017-05-17 08:44:52 +00:00
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//
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// OR
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//
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2017-05-31 15:15:24 +00:00
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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2017-05-29 06:55:41 +00:00
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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2015-06-26 09:04:19 +00:00
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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2017-04-13 08:45:54 +00:00
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module ad_lvds_out #(
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parameter DEVICE_TYPE = 0,
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parameter SINGLE_ENDED = 0,
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parameter IODELAY_ENABLE = 0,
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parameter IODELAY_CTRL = 0,
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parameter IODELAY_GROUP = "dev_if_delay_group") (
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2015-06-26 09:04:19 +00:00
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// data interface
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2017-04-13 08:45:54 +00:00
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input tx_clk,
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input tx_data_p,
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input tx_data_n,
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output tx_data_out_p,
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output tx_data_out_n,
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// delay-data interface
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2017-04-13 08:45:54 +00:00
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input up_clk,
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input up_dld,
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input [ 4:0] up_dwdata,
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output [ 4:0] up_drdata,
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// delay-cntrl interface
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2017-04-13 08:45:54 +00:00
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input delay_clk,
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input delay_rst,
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output delay_locked);
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2015-06-26 09:04:19 +00:00
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2016-09-30 15:52:00 +00:00
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localparam VIRTEX7 = 0;
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localparam VIRTEX6 = 1;
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localparam ULTRASCALE = 2;
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// internal signals
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wire tx_data_oddr_s;
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wire tx_data_odelay_s;
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// delay controller
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generate
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if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == VIRTEX7) && (IODELAY_CTRL == 1)) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYCTRL i_delay_ctrl (
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.RST (delay_rst),
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.REFCLK (delay_clk),
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.RDY (delay_locked));
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end else begin
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assign delay_locked = 1'b1;
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end
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endgenerate
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// transmit data interface, oddr -> odelay -> obuf
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2016-09-30 15:52:00 +00:00
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generate
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if (DEVICE_TYPE == ULTRASCALE) begin
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ODDRE1 i_tx_data_oddr (
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.SR (1'b0),
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.C (tx_clk),
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.D1 (tx_data_p),
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.D2 (tx_data_n),
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.Q (tx_data_oddr_s));
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end else begin
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ODDR #(
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.DDR_CLK_EDGE ("SAME_EDGE"),
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.INIT (1'b0),
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.SRTYPE ("ASYNC"))
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i_tx_data_oddr (
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.CE (1'b1),
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.R (1'b0),
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.S (1'b0),
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.C (tx_clk),
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.D1 (tx_data_p),
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.D2 (tx_data_n),
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.Q (tx_data_oddr_s));
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end
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endgenerate
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generate
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if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == VIRTEX7)) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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ODELAYE2 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("ODATAIN"),
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.HIGH_PERFORMANCE_MODE ("FALSE"),
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.ODELAY_TYPE ("VAR_LOAD"),
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.ODELAY_VALUE (0),
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.REFCLK_FREQUENCY (200.0),
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.PIPE_SEL ("FALSE"),
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.SIGNAL_PATTERN ("DATA"))
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i_tx_data_odelay (
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.CE (1'b0),
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.CLKIN (1'b0),
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.INC (1'b0),
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.LDPIPEEN (1'b0),
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.CINVCTRL (1'b0),
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.REGRST (1'b0),
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.C (up_clk),
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.ODATAIN (tx_data_oddr_s),
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.DATAOUT (tx_data_odelay_s),
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.LD (up_dld),
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.CNTVALUEIN (up_dwdata),
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.CNTVALUEOUT (up_drdata));
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end else begin
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assign up_drdata = 5'd0;
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assign tx_data_odelay_s = tx_data_oddr_s;
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end
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endgenerate
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2015-08-27 15:14:03 +00:00
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generate
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if (SINGLE_ENDED == 1) begin
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assign tx_data_out_n = 1'b0;
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OBUF i_tx_data_obuf (
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.I (tx_data_odelay_s),
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.O (tx_data_out_p));
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end else begin
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OBUFDS i_tx_data_obuf (
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.I (tx_data_odelay_s),
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.O (tx_data_out_p),
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.OB (tx_data_out_n));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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