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pluto_hdl_adi/docs/regmap/adi_regmap_dac.txt

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docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
TITLE
DAC Common (axi_ad)
DAC_COMMON
ENDTITLE
############################################################################################
############################################################################################
REG
0x0010
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
RSTN
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Interface Control & Status
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[2] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
CE_N
RW
Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of
the module to control clock enables
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[1] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
MMCM_RSTN
RW
MMCM reset only (required for DRP access).
Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RSTN
RW
Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0011
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
CNTRL_1
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Interface Control & Status
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
SYNC
RW
Setting this bit synchronizes channels within a DAC, and across multiple instances.
This bit self clears.
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[1] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
EXT_SYNC_ARM
RW
Setting this bit will arm the trigger mechanism sensitive to an external sync signal.
Once the external sync signal goes high it synchronizes channels within a DAC, and across multiple instances.
This bit has an effect only the EXT_SYNC synthesis parameter is set.
This bit self clears.
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[2] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
EXT_SYNC_DISARM
RW
Setting this bit will disarm the trigger mechanism sensitive to an external sync signal.
This bit has an effect only the EXT_SYNC synthesis parameter is set.
This bit self clears.
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[8] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
MANUAL_SYNC_REQUEST
RW
Setting this bit will issue an external sync event if it is hooked up inside the fabric.
This bit has an effect only the EXT_SYNC synthesis parameter is set.
This bit self clears.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0012
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
CNTRL_2
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Interface Control & Status
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[16] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
SDR_DDR_N
RW
Interface type (1 represents SDR, 0 represents DDR)
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
SYMB_OP
RW
Select data symbol format mode (0x1)
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[14] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
SYMB_8_16B
RW
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[12:8] 0x00000000
NUM_LANES
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane)
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[7] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
PAR_TYPE
RW
Select parity even (0x0) or odd (0x1).
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[6] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
PAR_ENB
RW
Select parity (0x1) or frame (0x0) mode.
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[5] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
R1_MODE
RW
Select number of RF channels 1 (0x1) or 2 (0x0).
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[4] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DATA_FORMAT
RW
Select data format 2's complement (0x0) or offset binary (0x1).
NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[3:0] 0x00000000
RESERVED
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
NA
Reserved
ENDFIELD
############################################################################################
############################################################################################
REG
0x0013
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
RATECNTRL
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Interface Control & Status
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[7:0] 0x00000000
RATE
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
The effective dac rate (the maximum possible rate is dependent on the interface clock).
The samples are generated at 1/RATE of the interface clock.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0014
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
FRAME
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Interface Control & Status
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
FRAME
RW
The use of frame is device specific. Usually setting this bit to 1 generates a FRAME (1
DCI clock period) pulse on the interface. This bit self clears.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0015
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
STATUS1
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Interface Control & Status
ENDREG
FIELD
[31:0] 0x00000000
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
CLK_FREQ
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RO
Interface clock frequency. This is relative to the processor clock and in many cases is
100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock
is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be
the same as the interface clock- software must consider device specific implementation
parameters to calculate the final sampling clock.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0016
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
STATUS2
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Interface Control & Status
ENDREG
FIELD
[31:0] 0x00000000
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
CLK_RATIO
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RO
Interface clock ratio - as a factor actual received clock. This is implementation specific
and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
ENDFIELD
############################################################################################
############################################################################################
REG
0x0017
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
STATUS3
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Interface Control & Status
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
STATUS
RO
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
Interface status, if set indicates no errors. If not set, there
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
are errors, software may try resetting the cores.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0018
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
DAC_CLKSEL
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Interface Control & Status
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC_CLKSEL
RW
Allows changing of the clock polarity. Note: its default value is CLK_EDGE_SEL
ENDFIELD
############################################################################################
############################################################################################
REG
0x001A
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
SYNC_STATUS
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Synchronization Status register
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC_SYNC_STATUS
RO
DAC synchronization status. Will be set to 1 while waiting for the external synchronization signal
This bit has an effect only the EXT_SYNC synthesis parameter is set.
ENDFIELD
############################################################################################
############################################################################################
REG
0x001C
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
DRP_CNTRL
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DRP Control & Status
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[28] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DRP_RWN
RW
DRP read (0x1) or write (0x0) select (does not include GTX lanes).
NOT-APPLICABLE if DRP_DISABLE is set (0x1).
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[27:16] 0x00000000
DRP_ADDRESS
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
DRP address, designs that contain more than one DRP accessible primitives
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
have selects based on the most significant bits (does not include GTX lanes).
NOT-APPLICABLE if DRP_DISABLE is set (0x1).
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:0] 0x00000000
RESERVED
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RO
Reserved for backwards compatibility
ENDFIELD
############################################################################################
############################################################################################
REG
0x001D
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
DRP_STATUS
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Interface Control & Status
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[17] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DRP_LOCKED
RO
If set indicates the MMCM/PLL is locked
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[16] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DRP_STATUS
RO
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
If set indicates busy (access pending). The read data may not be valid if
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
this bit is set (does not include GTX lanes).
NOT-APPLICABLE if DRP_DISABLE is set (0x1).
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:0] 0x00000000
RESERVED
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RO
Reserved for backwards compatibility
ENDFIELD
############################################################################################
############################################################################################
REG
0x001E
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
DRP_WDATA
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Interface Control & Status
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:0] 0x00000000
DRP_WDATA
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
DRP write data (does not include GTX lanes).
NOT-APPLICABLE if DRP_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
REG
0x001F
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
DRP_RDATA
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Interface Control & Status
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DRP_RDATA
RO
DRP read data (does not include GTX lanes).
NOT-APPLICABLE if DRP_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
library/common: Added DAC custom read/write interface in up_dac_common. The DAC common regmap was updated with 3 registers(rd/wr/ctrl) and 1 interface status flag for converters with custom control interface.
2023-02-20 12:33:45 +00:00
REG
0x0020
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
DAC_CUSTOM_RD
library/common: Added DAC custom read/write interface in up_dac_common. The DAC common regmap was updated with 3 registers(rd/wr/ctrl) and 1 interface status flag for converters with custom control interface.
2023-02-20 12:33:45 +00:00
DAC Read Configuration Data
ENDREG
FIELD
[31:0] 0x00000000
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
DAC_CUSTOM_RD
library/common: Added DAC custom read/write interface in up_dac_common. The DAC common regmap was updated with 3 registers(rd/wr/ctrl) and 1 interface status flag for converters with custom control interface.
2023-02-20 12:33:45 +00:00
RO
Custom Read of the available registers.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0021
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
DAC_CUSTOM_WR
library/common: Added DAC custom read/write interface in up_dac_common. The DAC common regmap was updated with 3 registers(rd/wr/ctrl) and 1 interface status flag for converters with custom control interface.
2023-02-20 12:33:45 +00:00
DAC Write Configuration Data
ENDREG
FIELD
[31:0] 0x00000000
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
DAC_CUSTOM_WR
library/common: Added DAC custom read/write interface in up_dac_common. The DAC common regmap was updated with 3 registers(rd/wr/ctrl) and 1 interface status flag for converters with custom control interface.
2023-02-20 12:33:45 +00:00
RW
Custom Write of the available registers.
ENDFIELD
############################################################################################
############################################################################################
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
REG
0x0022
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
UI_STATUS
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
User Interface Status
ENDREG
library/common: Added DAC custom read/write interface in up_dac_common. The DAC common regmap was updated with 3 registers(rd/wr/ctrl) and 1 interface status flag for converters with custom control interface.
2023-02-20 12:33:45 +00:00
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[4] 0x00000000
library/common: Added DAC custom read/write interface in up_dac_common. The DAC common regmap was updated with 3 registers(rd/wr/ctrl) and 1 interface status flag for converters with custom control interface.
2023-02-20 12:33:45 +00:00
IF_BUSY
RO
Interface busy. If set, indicates that the data interface is busy.
ENDFIELD
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[1] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
UI_OVF
RW1C
User Interface overflow. If set, indicates an overflow occurred during data transfer at
the user interface (FIFO interface). Software must write a 0x1 to clear this register
bit.
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
UI_UNF
RW1C
User Interface underflow. If set, indicates an underflow occurred during data transfer at
the user interface (FIFO interface). Software must write a 0x1 to clear this register
bit.
ENDFIELD
############################################################################################
############################################################################################
library/common: Added DAC custom read/write interface in up_dac_common. The DAC common regmap was updated with 3 registers(rd/wr/ctrl) and 1 interface status flag for converters with custom control interface.
2023-02-20 12:33:45 +00:00
REG
0x0023
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
DAC_CUSTOM_CTRL
library/common: Added DAC custom read/write interface in up_dac_common. The DAC common regmap was updated with 3 registers(rd/wr/ctrl) and 1 interface status flag for converters with custom control interface.
2023-02-20 12:33:45 +00:00
DAC Control Configuration Data
ENDREG
FIELD
[31:0] 0x00000000
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
DAC_CUSTOM_CTRL
library/common: Added DAC custom read/write interface in up_dac_common. The DAC common regmap was updated with 3 registers(rd/wr/ctrl) and 1 interface status flag for converters with custom control interface.
2023-02-20 12:33:45 +00:00
RW
Custom Control of the available registers.
ENDFIELD
############################################################################################
############################################################################################
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
REG
0x0028
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
USR_CNTRL_1
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC User Control & Status
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[7:0] 0x00000000
USR_CHANMAX
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
This indicates the maximum number of inputs for the channel data multiplexers. User may add
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
different processing modules as inputs to the dac.
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
REG
0x002E
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
DAC_GPIO_IN
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC GPIO inputs
ENDREG
FIELD
[31:0] 0x00000000
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
DAC_GPIO_IN
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RO
This reads auxiliary GPI pins of the DAC core
ENDFIELD
############################################################################################
############################################################################################
REG
0x002F
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
DAC_GPIO_OUT
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC GPIO outputs
ENDREG
FIELD
[31:0] 0x00000000
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
DAC_GPIO_OUT
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
This controls auxiliary GPO pins of the DAC core
NOT-APPLICABLE if GPIO_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
TITLE
DAC Channel (axi_ad*)
DAC_CHANNEL
ENDTITLE
############################################################################################
############################################################################################
REG
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
0x0100 + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_CNTRLn_1
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Channel Control & Status (channel - 0)
ENDREG
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[21:16] 0x00000000
DDS_PHASE_DW
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
R
The DDS phase data width offers the HDL parameter configuration with the same
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
name. This information is used in conjunction with CHAN_CNTRL_9 and CHAN_CNTRL_10.
More info at :ref:`ad_dds`.
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
ENDFIELD
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:0] 0x00000000
DDS_SCALE_1
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
The DDS scale for tone 1. Sets the amplitude of the tone. The format is 1.1.14
fixed point (signed, integer, fractional). The DDS in general runs on 16-bits,
note that if you do use both channels and set both scale to 0x4000, it is
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
over-range. The final output is (tone_1_fullscale * scale_1) +
(tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
ENDFIELD
############################################################################################
############################################################################################
REG
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
0x0101 + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_CNTRLn_2
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Channel Control & Status (channel - 0)
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:16] 0x00000000
DDS_INIT_1
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
The DDS phase initialization for tone 1. Sets the initial phase offset
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:0] 0x00000000
DDS_INCR_1
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
Sets the frequency of the phase accumulator. Its value can be calculated
by :math:`INCR = (f_{out} * 2^{16}) * clkratio / f_{if}`; where f_out is the
generated output frequency, and f_if is the frequency of the digital
interface, and clock_ratio is the ratio between the sampling clock and
the interface clock. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1),
the phase increment for tone 1 is extended in CHAN_CNTRL_9. NOT-APPLICABLE
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
if DDS_DISABLE is set (0x1).
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
ENDFIELD
############################################################################################
############################################################################################
REG
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
0x0102 + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_CNTRLn_3
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Channel Control & Status (channel - 0)
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:0] 0x00000000
DDS_SCALE_2
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
The DDS scale for tone 2. Sets the amplitude of the tone. The format
is 1.1.14 fixed point (signed, integer, fractional).
The DDS in general runs on 16-bits, note that if you do use both
channels and set both scale to 0x4000, it is over-range. The final
output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2).
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
NOT-APPLICABLE if DDS_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
REG
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
0x0103 + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_CNTRLn_4
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Channel Control & Status (channel - 0)
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:16] 0x00000000
DDS_INIT_2
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
The DDS phase initialization for tone 2. Sets the initial phase offset of the
tone. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase init
for tone 2 is extended in CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
set (0x1).
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:0] 0x00000000
DDS_INCR_2
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
Sets the frequency of the phase accumulator. Its value can be calculated by
:math:`INCR = (f_{out} * 2^{16}) * clkratio / f_{if}`; where f_out is the generated
output frequency, and f_if is the frequency of the digital interface, and
clock_ratio is the ratio between the sampling clock and the interface clock.
If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase increment
for tone 2 is extended in CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
set (0x1).
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
ENDFIELD
############################################################################################
############################################################################################
REG
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
0x0104 + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_CNTRLn_5
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Channel Control & Status (channel - 0)
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:16] 0x00000000
DDS_PATT_2
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
The DDS data pattern for this channel.
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:0] 0x00000000
DDS_PATT_1
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
The DDS data pattern for this channel.
ENDFIELD
############################################################################################
############################################################################################
REG
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
0x0105 + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_CNTRLn_6
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Channel Control & Status (channel - 0)
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[2] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
IQCOR_ENB
RW
if set, enables IQ correction.
NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[1] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC_LB_OWR
RW
If set, forces DAC_DDS_SEL to 0x8, loopback
If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[0] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC_PN_OWR
RW
IF set, forces DAC_DDS_SEL to 0x09, device specific pnX
If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
ENDFIELD
############################################################################################
############################################################################################
REG
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
0x0106 + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_CNTRLn_7
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Channel Control & Status (channel - 0)
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[3:0] 0x00000000
DAC_DDS_SEL
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
Select internal data sources (available only if the DAC supports it). \\
- 0x00: internal tone (DDS) \\
- 0x01: pattern (SED) \\
- 0x02: input data (DMA) \\
- 0x03: 0x00 \\
- 0x04: inverted pn7 \\
- 0x05: inverted pn15 \\
- 0x06: pn7 (standard O.150) \\
- 0x07: pn15 (standard O.150) \\
- 0x08: loopback data (ADC) \\
- 0x09: pnX (Device specific e.g. ad9361) \\
- 0x0A: Nibble ramp (Device specific e.g. adrv9001) \\
- 0x0B: 16 bit ramp (Device specific e.g. adrv9001) \\
ENDFIELD
############################################################################################
############################################################################################
REG
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
0x0107 + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_CNTRLn_8
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Channel Control & Status (channel - 0)
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:16] 0x00000000
IQCOR_COEFF_1
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value
and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used,
this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits).
NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:0] 0x00000000
IQCOR_COEFF_2
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value
and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient
and the format is 1.1.14 (sign, integer and fractional bits).
NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
REG
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
0x0108 + 0x16*n
WHERE n IS FROM 0 TO 15
USR_CNTRLn_3
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Channel Control & Status (channel - 0)
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[25] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
USR_DATATYPE_BE
RW
The user data type format- if set, indicates big endian (default is little endian).
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[24] 0x00000000
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
USR_DATATYPE_SIGNED
RW
The user data type format- if set, indicates signed (2's complement) data (default is unsigned).
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[23:16] 0x00000000
USR_DATATYPE_SHIFT
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
The user data type format- the amount of right shift for actual samples within the total number
of bits.
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:8] 0x00000000
USR_DATATYPE_TOTAL_BITS
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
The user data type format- number of total bits used for a sample. The total number of bits must
be an integer multiple of 8 (byte aligned).
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[7:0] 0x00000000
USR_DATATYPE_BITS
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
The user data type format- number of bits in a sample. This indicates the actual sample data bits.
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
REG
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
0x0109 + 0x16*n
WHERE n IS FROM 0 TO 15
USR_CNTRLn_4
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Channel Control & Status (channel - 0)
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:16] 0x00000000
USR_INTERPOLATION_M
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
This holds the user interpolation M value of the channel that is currently being
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
selected on the multiplexer above. The total interpolation factor is of the
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:0] 0x00000000
USR_INTERPOLATION_N
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
This holds the user interpolation N value of the channel that is currently being selected on
the multiplexer above. The total interpolation factor is of the form M/N.
NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
REG
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
0x010A + 0x16*n
WHERE n IS FROM 0 TO 15
USR_CNTRLn_5
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
DAC Channel Control & Status (channel - 0)
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[0] 0x00000000
DAC_IQ_MODE
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
Enable complex mode. In this mode the driven data to the DAC must be a sequence
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
of I and Q sample pairs.
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[1] 0x00000000
DAC_IQ_SWAP
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
RW
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
Allows IQ swapping in complex mode. Only takes effect if complex mode
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
is enabled.
ENDFIELD
############################################################################################
############################################################################################
REG
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
0x010B + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_CNTRLn_9
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
DAC Channel Control & Status (channel - 0)
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:16] 0x00000000
DDS_INIT_1_EXTENDED
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
RW
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
The extended DDS phase initialization for tone 1. Sets the initial phase offset
of the tone. The extended init(phase) value should be calculated according to
DDS_PHASE_DW value from CHAN_CNTRL_1 NOT-APPLICABLE if DDS_DISABLE is
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
set (0x1).
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:0] 0x00000000
DDS_INCR_1_EXTENDED
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
RW
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
Sets the frequency of tone 1's phase accumulator. Its value can be calculated
by :math:`INCR = (f_{out} * 2^{phaseDW}) * clkratio / f_{if}`; Where f_out is the
generated output frequency, DDS_PHASE_DW value can be found in CHAN_CNTRL_1
in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface,
and clock_ratio is the ratio between the sampling clock and the interface clock.
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
NOT-APPLICABLE if DDS_DISABLE is set (0x1).
ENDFIELD
############################################################################################
############################################################################################
REG
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
0x010C + 0x16*n
WHERE n IS FROM 0 TO 15
CHAN_CNTRLn_10
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
DAC Channel Control & Status (channel - 0)
ENDREG
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[31:16] 0x00000000
DDS_INIT_2_EXTENDED
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
RW
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
The extended DDS phase initialization for tone 2. Sets the initial phase offset
of the tone. The extended init(phase) value should be calculated according to
DDS_PHASE_DW value from CHAN_CNTRL_2 NOT-APPLICABLE if DDS_DISABLE is
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
set (0x1).
ENDFIELD
FIELD
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
[15:0] 0x00000000
DDS_INCR_2_EXTENDED
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
RW
docs: Intermediary for IP Cores import, user guide, regmap (#1321) Use interref (doctools cross-repository) to link the docs guidelines Add user guide pages, update IP references Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP", Update AXI DMAC, JESD204, I3C Controller, SPI Engines Minor fixes in the frameworks and register maps, the latter following the discussed guidelines. Update AXI terms to manager and subordinate. Signed-off-by: Jorge Marques <jorge.marques@analog.com> Signed-off-by: Laez Barbosa <laez.barbosa@analog.com> Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
Sets the frequency of tone 2's phase accumulator. Its value can be calculated
by :math:`INCR = (f_{out} * 2^{phaseDW}) * clkratio / f_{if}`; Where f_out is the
generated output frequency, DDS_PHASE_DW value can be found in CHAN_CNTRL_2
in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface,
and clock_ratio is the ratio between the sampling clock and the interface clock.
docs/regmap/adi_regmap_dac.txt : Updated and added some registers -Updated description of some fields of these registers: REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2, REG_CHAN_CNTRL_3, REG_CHAN_CNTRL_4, REG_USR_CNTRL_4, and REG_USR_CNTRL_5 -Added two new registers, both with their own fields and description: REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10 Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
2023-09-08 13:50:02 +00:00
NOT-APPLICABLE if DDS_DISABLE is set (0x1).
docs/regmap: Added ADI regmap_*.txt files (#1008)
2022-09-21 12:12:35 +00:00
ENDFIELD
############################################################################################
############################################################################################