2022-09-21 12:12:35 +00:00
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TITLE
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General Purpose Registers (axi_gpreg)
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AXI_GPREG
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
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0x0100 + 0x16*n
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WHERE n IS FROM 0 TO 15
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IO_ENBn
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2022-09-21 12:12:35 +00:00
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IO control register
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ENDREG
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FIELD
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[31:0] 0x00000000
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IO_ENB
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RW
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IO control register (use as tri-state control, logic depends on the buffer type).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
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0x0101 + 0x16*n
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WHERE n IS FROM 0 TO 15
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IO_OUTn
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2022-09-21 12:12:35 +00:00
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IO output register
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ENDREG
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FIELD
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[31:0] 0x00000000
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docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
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IO_OUT
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2022-09-21 12:12:35 +00:00
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RW
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IO output register.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
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0x0102 + 0x16*n
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WHERE n IS FROM 0 TO 15
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IO_INn
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2022-09-21 12:12:35 +00:00
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IO input register
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ENDREG
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FIELD
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[31:0] 0x00000000
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IO_IN
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RO
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IO input register.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
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0x0200 + 0x16*n
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WHERE n IS FROM 0 TO 15
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CM_RESETn
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2022-09-21 12:12:35 +00:00
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Reset register
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ENDREG
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FIELD
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docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
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[0] 0x00000000
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2022-09-21 12:12:35 +00:00
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CM_RESET_N
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RW
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Reset register (write a 0x01 to bring core out of reset).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
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0x0202 + 0x16*n
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WHERE n IS FROM 0 TO 15
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CM_COUNTn
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2022-09-21 12:12:35 +00:00
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Clock count register
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ENDREG
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FIELD
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[31:0] 0x00000000
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CM_CLK_COUNT
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RO
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Interface clock frequency. This is relative to the processor clock and in many cases is
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100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
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clock the minimum is 1.523kHz and maximum is 6.554THz.
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ENDFIELD
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############################################################################################
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############################################################################################
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