2015-01-06 13:39:13 +00:00
|
|
|
// ***************************************************************************
|
|
|
|
// ***************************************************************************
|
2023-07-06 13:54:40 +00:00
|
|
|
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
|
2015-01-06 13:39:13 +00:00
|
|
|
//
|
2017-05-31 15:15:24 +00:00
|
|
|
// In this HDL repository, there are many different and unique modules, consisting
|
|
|
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
|
|
|
// developed independently, and may be accompanied by separate and unique license
|
|
|
|
// terms.
|
|
|
|
//
|
|
|
|
// The user should read each of these license terms, and understand the
|
2018-03-14 14:45:47 +00:00
|
|
|
// freedoms and responsibilities that he or she has by using this source/core.
|
2017-05-31 15:15:24 +00:00
|
|
|
//
|
|
|
|
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
2017-05-29 06:55:41 +00:00
|
|
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
|
|
|
// A PARTICULAR PURPOSE.
|
2015-01-06 13:39:13 +00:00
|
|
|
//
|
2017-05-29 06:55:41 +00:00
|
|
|
// Redistribution and use of source or resulting binaries, with or without modification
|
|
|
|
// of this file, are permitted under one of the following two license terms:
|
2015-01-06 13:39:13 +00:00
|
|
|
//
|
2017-05-17 08:44:52 +00:00
|
|
|
// 1. The GNU General Public License version 2 as published by the
|
2017-05-31 15:15:24 +00:00
|
|
|
// Free Software Foundation, which can be found in the top level directory
|
|
|
|
// of this repository (LICENSE_GPL2), and also online at:
|
|
|
|
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
2017-05-17 08:44:52 +00:00
|
|
|
//
|
|
|
|
// OR
|
|
|
|
//
|
2017-05-31 15:15:24 +00:00
|
|
|
// 2. An ADI specific BSD license, which can be found in the top level directory
|
|
|
|
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
2023-12-13 16:03:34 +00:00
|
|
|
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
2017-05-29 06:55:41 +00:00
|
|
|
// This will allow to generate bit files and not release the source code,
|
|
|
|
// as long as it attaches to an ADI device.
|
2015-01-06 13:39:13 +00:00
|
|
|
//
|
|
|
|
// ***************************************************************************
|
|
|
|
// ***************************************************************************
|
|
|
|
// Transmit HDMI, CrYCb to RGB conversion
|
|
|
|
// The multiplication coefficients are in 1.4.12 format
|
|
|
|
// The addition coefficients are in 1.12.12 format
|
|
|
|
// R = (+408.583/256)*Cr + (+298.082/256)*Y + ( 000.000/256)*Cb + (-222.921);
|
|
|
|
// G = (-208.120/256)*Cr + (+298.082/256)*Y + (-100.291/256)*Cb + (+135.576);
|
|
|
|
// B = ( 000.000/256)*Cr + (+298.082/256)*Y + (+516.412/256)*Cb + (-276.836);
|
|
|
|
|
2018-08-27 07:14:54 +00:00
|
|
|
`timescale 1ns/100ps
|
|
|
|
|
2017-04-13 08:45:54 +00:00
|
|
|
module ad_csc_CrYCb2RGB #(
|
|
|
|
|
2022-04-08 10:21:52 +00:00
|
|
|
parameter DELAY_DATA_WIDTH = 16
|
|
|
|
) (
|
2015-01-06 13:39:13 +00:00
|
|
|
|
|
|
|
// Cr-Y-Cb inputs
|
|
|
|
|
2019-10-14 13:00:57 +00:00
|
|
|
input clk,
|
|
|
|
input [DELAY_DATA_WIDTH-1:0] CrYCb_sync,
|
|
|
|
input [23:0] CrYCb_data,
|
2015-01-06 13:39:13 +00:00
|
|
|
|
|
|
|
// R-G-B outputs
|
|
|
|
|
2019-10-14 13:00:57 +00:00
|
|
|
output [DELAY_DATA_WIDTH-1:0] RGB_sync,
|
2022-04-08 10:21:52 +00:00
|
|
|
output [23:0] RGB_data
|
|
|
|
);
|
2015-01-06 13:39:13 +00:00
|
|
|
|
|
|
|
localparam DW = DELAY_DATA_WIDTH - 1;
|
|
|
|
|
|
|
|
// red
|
|
|
|
|
2018-09-18 13:30:50 +00:00
|
|
|
ad_csc #(
|
|
|
|
.DELAY_DW (DELAY_DATA_WIDTH),
|
|
|
|
.MUL_COEF_DW (18),
|
|
|
|
.SUM_COEF_DW (28),
|
2022-04-08 10:21:52 +00:00
|
|
|
.YCbCr_2_RGB (1)
|
|
|
|
) i_csc_R (
|
2015-01-06 13:39:13 +00:00
|
|
|
.clk (clk),
|
|
|
|
.sync (CrYCb_sync),
|
|
|
|
.data (CrYCb_data),
|
2018-09-18 13:30:50 +00:00
|
|
|
.C1 ( 18'd52299),
|
|
|
|
.C2 ( 18'd38154),
|
|
|
|
.C3 ( 18'd0),
|
|
|
|
.C4 (-28'd7304675),
|
|
|
|
.csc_sync (RGB_sync),
|
|
|
|
.csc_data (RGB_data[23:16]));
|
2015-01-06 13:39:13 +00:00
|
|
|
|
|
|
|
// green
|
|
|
|
|
2018-09-18 13:30:50 +00:00
|
|
|
ad_csc #(
|
|
|
|
.MUL_COEF_DW (18),
|
|
|
|
.SUM_COEF_DW (28),
|
2022-04-08 10:21:52 +00:00
|
|
|
.YCbCr_2_RGB (1)
|
|
|
|
) i_csc_G (
|
2015-01-06 13:39:13 +00:00
|
|
|
.clk (clk),
|
2015-03-27 16:57:32 +00:00
|
|
|
.sync (1'd0),
|
2015-01-06 13:39:13 +00:00
|
|
|
.data (CrYCb_data),
|
2018-09-18 13:30:50 +00:00
|
|
|
.C1 (-18'd26639),
|
|
|
|
.C2 ( 18'd38154),
|
|
|
|
.C3 (-18'd12837),
|
|
|
|
.C4 ( 28'd4442554),
|
|
|
|
.csc_sync (),
|
|
|
|
.csc_data (RGB_data[15:8]));
|
2015-01-06 13:39:13 +00:00
|
|
|
|
|
|
|
// blue
|
|
|
|
|
2018-09-18 13:30:50 +00:00
|
|
|
ad_csc #(
|
|
|
|
.MUL_COEF_DW (18),
|
|
|
|
.SUM_COEF_DW (28),
|
2022-04-08 10:21:52 +00:00
|
|
|
.YCbCr_2_RGB (1)
|
|
|
|
) i_csc_B (
|
2015-01-06 13:39:13 +00:00
|
|
|
.clk (clk),
|
2015-03-27 16:57:32 +00:00
|
|
|
.sync (1'd0),
|
2015-01-06 13:39:13 +00:00
|
|
|
.data (CrYCb_data),
|
2018-09-18 13:30:50 +00:00
|
|
|
.C1 ( 18'd0),
|
|
|
|
.C2 ( 18'd38154),
|
|
|
|
.C3 ( 18'd66101),
|
|
|
|
.C4 (-28'd9071362),
|
|
|
|
.csc_sync (),
|
|
|
|
.csc_data (RGB_data[7:0]));
|
2015-01-06 13:39:13 +00:00
|
|
|
|
|
|
|
endmodule
|