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pluto_hdl_adi/projects/fmcadc5/vc707/system_bd.tcl

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Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb
2018-08-10 07:34:45 +00:00
## FIFO depth is 16Mb - 1M Samples
projects/system_bd- adc/dac fifo board designs
2017-02-27 21:05:21 +00:00
set adc_fifo_address_width 18
adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb
2018-08-10 07:34:45 +00:00
## NOTE: With this configuration the #36Kb BRAM utilization is at ~70%
renamed to match official names
2014-12-08 15:44:15 +00:00
source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
file renamed; sed output; fingers crossed
2017-02-22 20:56:37 +00:00
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
renamed to match official names
2014-12-08 15:44:15 +00:00
source ../common/fmcadc5_bd.tcl
sysid: Upgrade framework, header/ip are now at 2/1.1.a Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl add git branch to internal use area; update log prints; update xilixn projects; fix cn0506 sysid script;
2020-10-09 14:28:10 +00:00
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
renamed to match official names
2014-12-08 15:44:15 +00:00
Updated the makefiles to build the projects in subdirectories based on the build parameters. Running 'make' will build the default project directly in the project folder (like it did before) Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory. Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory. Running 'make clean' will clean the default project only. Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build. Running 'make clean-all' will delete all the built configurations and libraries. Note that the 'JESD' and 'LANE' words from the parameter names are stripped. Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-09-23 09:28:22 +00:00
set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
system_id: deployed ip
2019-06-28 08:41:21 +00:00
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
Updated the makefiles to build the projects in subdirectories based on the build parameters. Running 'make' will build the default project directly in the project folder (like it did before) Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory. Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory. Running 'make clean' will clean the default project only. Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build. Running 'make clean-all' will delete all the built configurations and libraries. Note that the 'JESD' and 'LANE' words from the parameter names are stripped. Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-09-23 09:28:22 +00:00
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
system_id: deployed ip
2019-06-28 08:41:21 +00:00
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid: Remove cstring init string
2020-09-28 21:10:35 +00:00
sysid_gen_sys_init_file
system_id: deployed ip
2019-06-28 08:41:21 +00:00
adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb
2018-08-10 07:34:45 +00:00
# ila
renamed to match official names
2014-12-08 15:44:15 +00:00
Ip automatic version update: fmcadc2, fmcadc5
2017-04-12 16:00:33 +00:00
ad_ip_instance util_mfifo mfifo_adc
ad_ip_parameter mfifo_adc CONFIG.NUM_OF_CHANNELS 1
ad_ip_parameter mfifo_adc CONFIG.DIN_DATA_WIDTH 512
ad_ip_parameter mfifo_adc CONFIG.ADDRESS_WIDTH 6
fmcadc5- added ila
2015-10-29 20:48:21 +00:00
Ip automatic version update: fmcadc2, fmcadc5
2017-04-12 16:00:33 +00:00
ad_ip_instance ila ila_adc
ad_ip_parameter ila_adc CONFIG.C_MONITOR_TYPE Native
ad_ip_parameter ila_adc CONFIG.C_TRIGIN_EN false
ad_ip_parameter ila_adc CONFIG.C_EN_STRG_QUAL 1
ad_ip_parameter ila_adc CONFIG.C_NUM_OF_PROBES 2
ad_ip_parameter ila_adc CONFIG.C_PROBE0_WIDTH 1
ad_ip_parameter ila_adc CONFIG.C_PROBE1_WIDTH 16
fmcadc5- added ila
2015-10-29 20:48:21 +00:00
fmcadc5- replaced with axi_adxcvr
2016-11-23 21:21:57 +00:00
ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 mfifo_adc/din_clk
ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset mfifo_adc/din_rst
fmcadc5- syntax/port name fixes
2017-05-10 20:30:15 +00:00
ad_connect axi_fmcadc5_sync/rx_enable mfifo_adc/din_valid
ad_connect axi_fmcadc5_sync/rx_data mfifo_adc/din_data_0
fmcadc5- replaced with axi_adxcvr
2016-11-23 21:21:57 +00:00
ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset mfifo_adc/dout_rst
ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 mfifo_adc/dout_clk
ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 ila_adc/clk
fmcadc5- added ila
2015-10-29 20:48:21 +00:00
ad_connect mfifo_adc/dout_valid ila_adc/probe0
ad_connect mfifo_adc/dout_data_0 ila_adc/probe1
fmcadc5: add programmable io delay
2015-11-02 17:10:08 +00:00