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pluto_hdl_adi/projects/adrv9009/zcu102/system_bd.tcl

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Renamed ad9379 to adrv9009
2018-04-25 13:02:59 +00:00
adrv9009/zcu102: Increase DAC buffer depth to 18Mb
2018-09-05 08:32:28 +00:00
## FIFO depth is 18Mb - 1M samples
set dac_fifo_address_width 17
Renamed ad9379 to adrv9009
2018-04-25 13:02:59 +00:00
adrv9009/zcu102: Increase DAC buffer depth to 18Mb
2018-09-05 08:32:28 +00:00
## NOTE: With this configuration the #36Kb BRAM utilization is at ~57%
Renamed ad9379 to adrv9009
2018-04-25 13:02:59 +00:00
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
sysid: Upgrade framework, header/ip are now at 2/1.1.a Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl add git branch to internal use area; update log prints; update xilixn projects; fix cn0506 sysid script;
2020-10-09 14:28:10 +00:00
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
Renamed ad9379 to adrv9009
2018-04-25 13:02:59 +00:00
system_id: deployed ip
2019-06-28 08:41:21 +00:00
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid: Remove cstring init string
2020-09-28 21:10:35 +00:00
sysid_gen_sys_init_file
system_id: deployed ip
2019-06-28 08:41:21 +00:00
adrv9009: Improved data throughput and DAC FIFO size Moved XCVR related connections to HP0, where the HP shares the MUX with the Video DMA HP1 and HP2 are used for RX OS and RX DMAs, sharing the MUX. Usually they shouldn't run at the same time. HP3 is used for TX DMA, sharing the MUX with the FPD DMA controller All HPx and DMA buswidths have been increased to 128 bits The HPx-DMA clock has been increased to 300 MHz DAC FIFO address size has been increased to 17
2018-05-11 12:01:05 +00:00
ad_mem_hp0_interconnect sys_cpu_clk sys_ps8/S_AXI_HP0
Renamed ad9379 to adrv9009
2018-04-25 13:02:59 +00:00
source ../common/adrv9009_bd.tcl
adrv9009: Improved data throughput and DAC FIFO size Moved XCVR related connections to HP0, where the HP shares the MUX with the Video DMA HP1 and HP2 are used for RX OS and RX DMAs, sharing the MUX. Usually they shouldn't run at the same time. HP3 is used for TX DMA, sharing the MUX with the FPD DMA controller All HPx and DMA buswidths have been increased to 128 bits The HPx-DMA clock has been increased to 300 MHz DAC FIFO address size has been increased to 17
2018-05-11 12:01:05 +00:00
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_DATA_WIDTH_DEST 128
adrv9009: Increase DMA FIFO sizes
2018-05-24 06:38:59 +00:00
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.FIFO_SIZE 32
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.FIFO_SIZE 32
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.FIFO_SIZE 32
adrv9009: Improved data throughput and DAC FIFO size Moved XCVR related connections to HP0, where the HP shares the MUX with the Video DMA HP1 and HP2 are used for RX OS and RX DMAs, sharing the MUX. Usually they shouldn't run at the same time. HP3 is used for TX DMA, sharing the MUX with the FPD DMA controller All HPx and DMA buswidths have been increased to 128 bits The HPx-DMA clock has been increased to 300 MHz DAC FIFO address size has been increased to 17
2018-05-11 12:01:05 +00:00
Renamed ad9379 to adrv9009
2018-04-25 13:02:59 +00:00
ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_FBDIV 80
ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_REFCLK_DIV 1