611 lines
18 KiB
Coq
611 lines
18 KiB
Coq
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// -------------------------------------------------------------
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//
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// Module: cic_decim
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// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0.
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// Generated on: 2016-07-05 15:46:18
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// -------------------------------------------------------------
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// -------------------------------------------------------------
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// HDL Code Generation Options:
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//
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// OptimizeForHDL: on
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// EDAScriptGeneration: off
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// AddPipelineRegisters: on
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// Name: cic_decim
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// AddRatePort: on
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// InputDataType: numerictype(1,12,11)
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// TargetLanguage: Verilog
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// TestBenchName: cicdecimfilt_copy_tb
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// TestBenchStimulus: step ramp chirp noise
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// GenerateHDLTestBench: off
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// -------------------------------------------------------------
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// HDL Implementation : Fully parallel
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// -------------------------------------------------------------
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// Filter Settings:
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//
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// Discrete-Time FIR Multirate Filter (real)
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// -----------------------------------------
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// Filter Structure : Cascaded Integrator-Comb Decimator
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// Decimation Factor : 50000
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// Differential Delay : 1
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// Number of Sections : 6
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// Stable : Yes
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// Linear Phase : No
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//
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// -------------------------------------------------------------
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`timescale 1 ns / 1 ns
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module cic_decim
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(
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clk,
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clk_enable,
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reset,
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filter_in,
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rate,
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load_rate,
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filter_out,
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ce_out
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);
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input clk;
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input clk_enable;
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input reset;
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input signed [11:0] filter_in; //sfix12_En11
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input [15:0] rate; //ufix16
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input load_rate;
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output signed [105:0] filter_out; //sfix106_En11
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output ce_out;
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////////////////////////////////////////////////////////////////
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//Module Architecture: cic_decim
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////////////////////////////////////////////////////////////////
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// Local Functions
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// Type Definitions
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// Constants
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// Signals
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reg [15:0] rate_register; // ufix16
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reg [15:0] cur_count; // ufix16
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wire phase_1; // boolean
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wire ce_delayline; // boolean
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reg int_delay_pipe [0:4] ; // boolean
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wire ce_gated; // boolean
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reg ce_out_reg; // boolean
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//
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reg signed [11:0] input_register; // sfix12_En11
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// -- Section 1 Signals
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wire signed [11:0] section_in1; // sfix12_En11
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wire signed [105:0] section_cast1; // sfix106_En11
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wire signed [105:0] sum1; // sfix106_En11
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reg signed [105:0] section_out1; // sfix106_En11
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wire signed [105:0] add_cast; // sfix106_En11
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wire signed [105:0] add_cast_1; // sfix106_En11
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wire signed [106:0] add_temp; // sfix107_En11
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// -- Section 2 Signals
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wire signed [105:0] section_in2; // sfix106_En11
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wire signed [105:0] sum2; // sfix106_En11
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reg signed [105:0] section_out2; // sfix106_En11
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wire signed [105:0] add_cast_2; // sfix106_En11
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wire signed [105:0] add_cast_3; // sfix106_En11
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wire signed [106:0] add_temp_1; // sfix107_En11
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// -- Section 3 Signals
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wire signed [105:0] section_in3; // sfix106_En11
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wire signed [105:0] sum3; // sfix106_En11
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reg signed [105:0] section_out3; // sfix106_En11
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wire signed [105:0] add_cast_4; // sfix106_En11
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wire signed [105:0] add_cast_5; // sfix106_En11
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wire signed [106:0] add_temp_2; // sfix107_En11
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// -- Section 4 Signals
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wire signed [105:0] section_in4; // sfix106_En11
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wire signed [105:0] sum4; // sfix106_En11
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reg signed [105:0] section_out4; // sfix106_En11
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wire signed [105:0] add_cast_6; // sfix106_En11
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wire signed [105:0] add_cast_7; // sfix106_En11
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wire signed [106:0] add_temp_3; // sfix107_En11
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// -- Section 5 Signals
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wire signed [105:0] section_in5; // sfix106_En11
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wire signed [105:0] sum5; // sfix106_En11
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reg signed [105:0] section_out5; // sfix106_En11
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wire signed [105:0] add_cast_8; // sfix106_En11
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wire signed [105:0] add_cast_9; // sfix106_En11
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wire signed [106:0] add_temp_4; // sfix107_En11
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// -- Section 6 Signals
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wire signed [105:0] section_in6; // sfix106_En11
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wire signed [105:0] sum6; // sfix106_En11
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reg signed [105:0] section_out6; // sfix106_En11
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wire signed [105:0] add_cast_10; // sfix106_En11
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wire signed [105:0] add_cast_11; // sfix106_En11
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wire signed [106:0] add_temp_5; // sfix107_En11
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// -- Section 7 Signals
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wire signed [105:0] section_in7; // sfix106_En11
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reg signed [105:0] diff1; // sfix106_En11
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wire signed [105:0] section_out7; // sfix106_En11
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wire signed [105:0] sub_cast; // sfix106_En11
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wire signed [105:0] sub_cast_1; // sfix106_En11
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wire signed [106:0] sub_temp; // sfix107_En11
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reg signed [105:0] cic_pipeline7; // sfix106_En11
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// -- Section 8 Signals
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wire signed [105:0] section_in8; // sfix106_En11
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reg signed [105:0] diff2; // sfix106_En11
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wire signed [105:0] section_out8; // sfix106_En11
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wire signed [105:0] sub_cast_2; // sfix106_En11
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wire signed [105:0] sub_cast_3; // sfix106_En11
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wire signed [106:0] sub_temp_1; // sfix107_En11
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reg signed [105:0] cic_pipeline8; // sfix106_En11
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// -- Section 9 Signals
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wire signed [105:0] section_in9; // sfix106_En11
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reg signed [105:0] diff3; // sfix106_En11
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wire signed [105:0] section_out9; // sfix106_En11
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wire signed [105:0] sub_cast_4; // sfix106_En11
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wire signed [105:0] sub_cast_5; // sfix106_En11
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wire signed [106:0] sub_temp_2; // sfix107_En11
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reg signed [105:0] cic_pipeline9; // sfix106_En11
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// -- Section 10 Signals
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wire signed [105:0] section_in10; // sfix106_En11
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reg signed [105:0] diff4; // sfix106_En11
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wire signed [105:0] section_out10; // sfix106_En11
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wire signed [105:0] sub_cast_6; // sfix106_En11
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wire signed [105:0] sub_cast_7; // sfix106_En11
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wire signed [106:0] sub_temp_3; // sfix107_En11
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reg signed [105:0] cic_pipeline10; // sfix106_En11
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// -- Section 11 Signals
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wire signed [105:0] section_in11; // sfix106_En11
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reg signed [105:0] diff5; // sfix106_En11
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wire signed [105:0] section_out11; // sfix106_En11
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wire signed [105:0] sub_cast_8; // sfix106_En11
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wire signed [105:0] sub_cast_9; // sfix106_En11
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wire signed [106:0] sub_temp_4; // sfix107_En11
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reg signed [105:0] cic_pipeline11; // sfix106_En11
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// -- Section 12 Signals
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wire signed [105:0] section_in12; // sfix106_En11
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reg signed [105:0] diff6; // sfix106_En11
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wire signed [105:0] section_out12; // sfix106_En11
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wire signed [105:0] sub_cast_10; // sfix106_En11
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wire signed [105:0] sub_cast_11; // sfix106_En11
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wire signed [106:0] sub_temp_5; // sfix107_En11
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reg [6:0] bitgain; // ufix7
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wire signed [105:0] output_typeconvert; // sfix106_En11
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wire signed [105:0] muxinput_14; // sfix106_E3
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wire signed [105:0] muxinput_34; // sfix106_E23
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wire signed [105:0] muxinput_54; // sfix106_E43
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wire signed [105:0] muxinput_74; // sfix106_E63
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wire signed [105:0] muxinput_94; // sfix106_E83
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//
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reg signed [105:0] output_register; // sfix106_En11
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// Block Statements
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// ------------------ CE Output Generation ------------------
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always @ (posedge clk or posedge reset)
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begin: ce_output
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if (reset == 1'b1) begin
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cur_count <= 16'b0000000000000000;
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end
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else begin
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if (clk_enable == 1'b1) begin
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if (load_rate == 1'b1) begin
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cur_count <= 16'b0000000000000001;
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end
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else if (cur_count == rate_register - 1) begin
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cur_count <= 16'b0000000000000000;
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end
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else begin
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cur_count <= cur_count + 1;
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end
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end
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end
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end // ce_output
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assign phase_1 = (cur_count == 16'b0000000000000001 && clk_enable == 1'b1)? 1 : 0;
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always @ (posedge clk or posedge reset)
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begin: ce_delay
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if (reset == 1'b1) begin
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int_delay_pipe[0] <= 1'b0;
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int_delay_pipe[1] <= 1'b0;
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int_delay_pipe[2] <= 1'b0;
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int_delay_pipe[3] <= 1'b0;
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int_delay_pipe[4] <= 1'b0;
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end
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else begin
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if (phase_1 == 1'b1) begin
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int_delay_pipe[1] <= int_delay_pipe[0];
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int_delay_pipe[2] <= int_delay_pipe[1];
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int_delay_pipe[3] <= int_delay_pipe[2];
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int_delay_pipe[4] <= int_delay_pipe[3];
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int_delay_pipe[0] <= clk_enable;
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end
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end
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end // ce_delay
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assign ce_delayline = int_delay_pipe[4];
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assign ce_gated = ce_delayline & phase_1;
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// ------------------ CE Output Register ------------------
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always @ (posedge clk or posedge reset)
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begin: ce_output_register
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if (reset == 1'b1) begin
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ce_out_reg <= 1'b0;
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end
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else begin
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ce_out_reg <= ce_gated;
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end
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end // ce_output_register
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// ------------------ Input Register ------------------
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always @ (posedge clk or posedge reset)
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begin: input_reg_process
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if (reset == 1'b1) begin
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input_register <= 0;
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rate_register <= 0;
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end
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else begin
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if (clk_enable == 1'b1) begin
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input_register <= filter_in;
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rate_register <= rate;
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end
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end
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end // input_reg_process
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// ------------------ Section # 1 : Integrator ------------------
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assign section_in1 = input_register;
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assign section_cast1 = $signed({{94{section_in1[11]}}, section_in1});
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assign add_cast = section_cast1;
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assign add_cast_1 = section_out1;
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assign add_temp = add_cast + add_cast_1;
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assign sum1 = add_temp[105:0];
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always @ (posedge clk or posedge reset)
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begin: integrator_delay_section1
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if (reset == 1'b1) begin
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section_out1 <= 0;
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end
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else begin
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if (clk_enable == 1'b1) begin
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section_out1 <= sum1;
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end
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end
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end // integrator_delay_section1
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// ------------------ Section # 2 : Integrator ------------------
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assign section_in2 = section_out1;
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assign add_cast_2 = section_in2;
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assign add_cast_3 = section_out2;
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assign add_temp_1 = add_cast_2 + add_cast_3;
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assign sum2 = add_temp_1[105:0];
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always @ (posedge clk or posedge reset)
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begin: integrator_delay_section2
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if (reset == 1'b1) begin
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section_out2 <= 0;
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end
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else begin
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if (clk_enable == 1'b1) begin
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section_out2 <= sum2;
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end
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end
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end // integrator_delay_section2
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// ------------------ Section # 3 : Integrator ------------------
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assign section_in3 = section_out2;
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assign add_cast_4 = section_in3;
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assign add_cast_5 = section_out3;
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assign add_temp_2 = add_cast_4 + add_cast_5;
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assign sum3 = add_temp_2[105:0];
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always @ (posedge clk or posedge reset)
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begin: integrator_delay_section3
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if (reset == 1'b1) begin
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section_out3 <= 0;
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end
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else begin
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if (clk_enable == 1'b1) begin
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section_out3 <= sum3;
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end
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end
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end // integrator_delay_section3
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// ------------------ Section # 4 : Integrator ------------------
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assign section_in4 = section_out3;
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assign add_cast_6 = section_in4;
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assign add_cast_7 = section_out4;
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assign add_temp_3 = add_cast_6 + add_cast_7;
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assign sum4 = add_temp_3[105:0];
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always @ (posedge clk or posedge reset)
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begin: integrator_delay_section4
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if (reset == 1'b1) begin
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section_out4 <= 0;
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end
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else begin
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if (clk_enable == 1'b1) begin
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section_out4 <= sum4;
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end
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end
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end // integrator_delay_section4
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// ------------------ Section # 5 : Integrator ------------------
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assign section_in5 = section_out4;
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assign add_cast_8 = section_in5;
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assign add_cast_9 = section_out5;
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assign add_temp_4 = add_cast_8 + add_cast_9;
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|
assign sum5 = add_temp_4[105:0];
|
||
|
|
|
||
|
|
always @ (posedge clk or posedge reset)
|
||
|
|
begin: integrator_delay_section5
|
||
|
|
if (reset == 1'b1) begin
|
||
|
|
section_out5 <= 0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
if (clk_enable == 1'b1) begin
|
||
|
|
section_out5 <= sum5;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end // integrator_delay_section5
|
||
|
|
|
||
|
|
// ------------------ Section # 6 : Integrator ------------------
|
||
|
|
|
||
|
|
assign section_in6 = section_out5;
|
||
|
|
|
||
|
|
assign add_cast_10 = section_in6;
|
||
|
|
assign add_cast_11 = section_out6;
|
||
|
|
assign add_temp_5 = add_cast_10 + add_cast_11;
|
||
|
|
assign sum6 = add_temp_5[105:0];
|
||
|
|
|
||
|
|
always @ (posedge clk or posedge reset)
|
||
|
|
begin: integrator_delay_section6
|
||
|
|
if (reset == 1'b1) begin
|
||
|
|
section_out6 <= 0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
if (clk_enable == 1'b1) begin
|
||
|
|
section_out6 <= sum6;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end // integrator_delay_section6
|
||
|
|
|
||
|
|
// ------------------ Section # 7 : Comb ------------------
|
||
|
|
|
||
|
|
assign section_in7 = section_out6;
|
||
|
|
|
||
|
|
assign sub_cast = section_in7;
|
||
|
|
assign sub_cast_1 = diff1;
|
||
|
|
assign sub_temp = sub_cast - sub_cast_1;
|
||
|
|
assign section_out7 = sub_temp[105:0];
|
||
|
|
|
||
|
|
always @ (posedge clk or posedge reset)
|
||
|
|
begin: comb_delay_section7
|
||
|
|
if (reset == 1'b1) begin
|
||
|
|
diff1 <= 0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
if (phase_1 == 1'b1) begin
|
||
|
|
diff1 <= section_in7;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end // comb_delay_section7
|
||
|
|
|
||
|
|
always @ (posedge clk or posedge reset)
|
||
|
|
begin: cic_pipeline_process_section7
|
||
|
|
if (reset == 1'b1) begin
|
||
|
|
cic_pipeline7 <= 0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
if (phase_1 == 1'b1) begin
|
||
|
|
cic_pipeline7 <= section_out7;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end // cic_pipeline_process_section7
|
||
|
|
|
||
|
|
// ------------------ Section # 8 : Comb ------------------
|
||
|
|
|
||
|
|
assign section_in8 = cic_pipeline7;
|
||
|
|
|
||
|
|
assign sub_cast_2 = section_in8;
|
||
|
|
assign sub_cast_3 = diff2;
|
||
|
|
assign sub_temp_1 = sub_cast_2 - sub_cast_3;
|
||
|
|
assign section_out8 = sub_temp_1[105:0];
|
||
|
|
|
||
|
|
always @ (posedge clk or posedge reset)
|
||
|
|
begin: comb_delay_section8
|
||
|
|
if (reset == 1'b1) begin
|
||
|
|
diff2 <= 0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
if (phase_1 == 1'b1) begin
|
||
|
|
diff2 <= section_in8;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end // comb_delay_section8
|
||
|
|
|
||
|
|
always @ (posedge clk or posedge reset)
|
||
|
|
begin: cic_pipeline_process_section8
|
||
|
|
if (reset == 1'b1) begin
|
||
|
|
cic_pipeline8 <= 0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
if (phase_1 == 1'b1) begin
|
||
|
|
cic_pipeline8 <= section_out8;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end // cic_pipeline_process_section8
|
||
|
|
|
||
|
|
// ------------------ Section # 9 : Comb ------------------
|
||
|
|
|
||
|
|
assign section_in9 = cic_pipeline8;
|
||
|
|
|
||
|
|
assign sub_cast_4 = section_in9;
|
||
|
|
assign sub_cast_5 = diff3;
|
||
|
|
assign sub_temp_2 = sub_cast_4 - sub_cast_5;
|
||
|
|
assign section_out9 = sub_temp_2[105:0];
|
||
|
|
|
||
|
|
always @ (posedge clk or posedge reset)
|
||
|
|
begin: comb_delay_section9
|
||
|
|
if (reset == 1'b1) begin
|
||
|
|
diff3 <= 0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
if (phase_1 == 1'b1) begin
|
||
|
|
diff3 <= section_in9;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end // comb_delay_section9
|
||
|
|
|
||
|
|
always @ (posedge clk or posedge reset)
|
||
|
|
begin: cic_pipeline_process_section9
|
||
|
|
if (reset == 1'b1) begin
|
||
|
|
cic_pipeline9 <= 0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
if (phase_1 == 1'b1) begin
|
||
|
|
cic_pipeline9 <= section_out9;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end // cic_pipeline_process_section9
|
||
|
|
|
||
|
|
// ------------------ Section # 10 : Comb ------------------
|
||
|
|
|
||
|
|
assign section_in10 = cic_pipeline9;
|
||
|
|
|
||
|
|
assign sub_cast_6 = section_in10;
|
||
|
|
assign sub_cast_7 = diff4;
|
||
|
|
assign sub_temp_3 = sub_cast_6 - sub_cast_7;
|
||
|
|
assign section_out10 = sub_temp_3[105:0];
|
||
|
|
|
||
|
|
always @ (posedge clk or posedge reset)
|
||
|
|
begin: comb_delay_section10
|
||
|
|
if (reset == 1'b1) begin
|
||
|
|
diff4 <= 0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
if (phase_1 == 1'b1) begin
|
||
|
|
diff4 <= section_in10;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end // comb_delay_section10
|
||
|
|
|
||
|
|
always @ (posedge clk or posedge reset)
|
||
|
|
begin: cic_pipeline_process_section10
|
||
|
|
if (reset == 1'b1) begin
|
||
|
|
cic_pipeline10 <= 0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
if (phase_1 == 1'b1) begin
|
||
|
|
cic_pipeline10 <= section_out10;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end // cic_pipeline_process_section10
|
||
|
|
|
||
|
|
// ------------------ Section # 11 : Comb ------------------
|
||
|
|
|
||
|
|
assign section_in11 = cic_pipeline10;
|
||
|
|
|
||
|
|
assign sub_cast_8 = section_in11;
|
||
|
|
assign sub_cast_9 = diff5;
|
||
|
|
assign sub_temp_4 = sub_cast_8 - sub_cast_9;
|
||
|
|
assign section_out11 = sub_temp_4[105:0];
|
||
|
|
|
||
|
|
always @ (posedge clk or posedge reset)
|
||
|
|
begin: comb_delay_section11
|
||
|
|
if (reset == 1'b1) begin
|
||
|
|
diff5 <= 0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
if (phase_1 == 1'b1) begin
|
||
|
|
diff5 <= section_in11;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end // comb_delay_section11
|
||
|
|
|
||
|
|
always @ (posedge clk or posedge reset)
|
||
|
|
begin: cic_pipeline_process_section11
|
||
|
|
if (reset == 1'b1) begin
|
||
|
|
cic_pipeline11 <= 0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
if (phase_1 == 1'b1) begin
|
||
|
|
cic_pipeline11 <= section_out11;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end // cic_pipeline_process_section11
|
||
|
|
|
||
|
|
// ------------------ Section # 12 : Comb ------------------
|
||
|
|
|
||
|
|
assign section_in12 = cic_pipeline11;
|
||
|
|
|
||
|
|
assign sub_cast_10 = section_in12;
|
||
|
|
assign sub_cast_11 = diff6;
|
||
|
|
assign sub_temp_5 = sub_cast_10 - sub_cast_11;
|
||
|
|
assign section_out12 = sub_temp_5[105:0];
|
||
|
|
|
||
|
|
always @ (posedge clk or posedge reset)
|
||
|
|
begin: comb_delay_section12
|
||
|
|
if (reset == 1'b1) begin
|
||
|
|
diff6 <= 0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
if (phase_1 == 1'b1) begin
|
||
|
|
diff6 <= section_in12;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end // comb_delay_section12
|
||
|
|
|
||
|
|
always @(rate_register)
|
||
|
|
begin
|
||
|
|
case(rate_register)
|
||
|
|
16'b0000000000000101 : bitgain = 7'b0001110;
|
||
|
|
16'b0000000000110010 : bitgain = 7'b0100010;
|
||
|
|
16'b0000000111110100 : bitgain = 7'b0110110;
|
||
|
|
16'b0001001110001000 : bitgain = 7'b1001010;
|
||
|
|
default : bitgain = 7'b1011110;
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign muxinput_14 = $signed({{14{section_out12[105]}}, section_out12[105:14]});
|
||
|
|
|
||
|
|
assign muxinput_34 = $signed({{34{section_out12[105]}}, section_out12[105:34]});
|
||
|
|
|
||
|
|
assign muxinput_54 = $signed({{54{section_out12[105]}}, section_out12[105:54]});
|
||
|
|
|
||
|
|
assign muxinput_74 = $signed({{74{section_out12[105]}}, section_out12[105:74]});
|
||
|
|
|
||
|
|
assign muxinput_94 = $signed({{94{section_out12[105]}}, section_out12[105:94]});
|
||
|
|
|
||
|
|
assign output_typeconvert = (bitgain == 7'b0001110) ? muxinput_14 :
|
||
|
|
(bitgain == 7'b0100010) ? muxinput_34 :
|
||
|
|
(bitgain == 7'b0110110) ? muxinput_54 :
|
||
|
|
(bitgain == 7'b1001010) ? muxinput_74 :
|
||
|
|
muxinput_94;
|
||
|
|
// ------------------ Output Register ------------------
|
||
|
|
|
||
|
|
always @ (posedge clk or posedge reset)
|
||
|
|
begin: output_reg_process
|
||
|
|
if (reset == 1'b1) begin
|
||
|
|
output_register <= 0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
if (phase_1 == 1'b1) begin
|
||
|
|
output_register <= output_typeconvert;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end // output_reg_process
|
||
|
|
|
||
|
|
// Assignment Statements
|
||
|
|
assign ce_out = ce_out_reg;
|
||
|
|
assign filter_out = output_register;
|
||
|
|
endmodule // cic_decim
|