pluto_hdl_adi/projects/adrv9371x/zcu102/system_bd.tcl

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Tcl
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2017-08-22 12:48:03 +00:00
set dac_fifo_name axi_ad9371_dacfifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 150
source ../common/adrv9371x_bd.tcl
ad_connect sys_dma_clk sys_ps8/pl_clk2
ad_connect sys_dma_rstgen/ext_reset_in sys_rstgen/peripheral_reset
ad_ip_parameter util_ad9371_xcvr CONFIG.XCVR_TYPE 2
ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_FBDIV 20
ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_REFCLK_DIV 1