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pluto_hdl_adi/projects/fmcadc5/common/fmcadc5_bd.tcl

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Merge branch 'hdl_2014_r2' into dev Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.v
2014-12-08 16:32:13 +00:00
# ad9625
fmcadc5: 2014.4 updates
2015-03-23 14:00:20 +00:00
create_bd_port -dir I rx_ref_clk_0
create_bd_port -dir I -from 7 -to 0 rx_data_0_p
create_bd_port -dir I -from 7 -to 0 rx_data_0_n
create_bd_port -dir O rx_sync_0
create_bd_port -dir I rx_ref_clk_1
create_bd_port -dir I -from 7 -to 0 rx_data_1_p
create_bd_port -dir I -from 7 -to 0 rx_data_1_n
create_bd_port -dir O rx_sync_1
fmcadc5- gt/ip updates
2015-10-15 20:05:15 +00:00
create_bd_port -dir O rx_sysref
fmcadc5: add programmable io delay
2015-11-02 17:10:08 +00:00
create_bd_port -dir O rx_clk
Merge branch 'hdl_2014_r2' into dev Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.v
2014-12-08 16:32:13 +00:00
# adc peripherals
set axi_ad9625_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_0_core]
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.ID {0}] $axi_ad9625_0_core
Merge branch 'hdl_2014_r2' into dev Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.v
2014-12-08 16:32:13 +00:00
set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core]
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.ID {1}] $axi_ad9625_1_core
Merge branch 'hdl_2014_r2' into dev Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.v
2014-12-08 16:32:13 +00:00
fmcadc5/common: Update common design to 2015.4
2016-04-14 20:01:38 +00:00
set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_0_jesd]
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_0_jesd
fmcadc5/common: Update common design to 2015.4
2016-04-14 20:01:38 +00:00
set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_1_jesd]
Merge branch 'hdl_2014_r2' into dev Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.v
2014-12-08 16:32:13 +00:00
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_1_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_1_jesd
set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma]
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.ID {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9625_dma
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
Merge branch 'hdl_2014_r2' into dev Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.v
2014-12-08 16:32:13 +00:00
p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 512 18
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
# adc common gt
set axi_fmcadc5_0_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc5_0_gt]
set_property -dict [list CONFIG.ID {0}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
set axi_fmcadc5_1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc5_1_gt]
fmcadc5- gt/ip updates
2015-10-15 20:05:15 +00:00
set_property -dict [list CONFIG.ID {1}] $axi_fmcadc5_1_gt
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
set util_fmcadc5_0_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcadc5_0_gt]
set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcadc5_0_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_0_gt
set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcadc5_0_gt
set util_fmcadc5_1_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcadc5_1_gt]
set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcadc5_1_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_1_gt
set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcadc5_1_gt
set axi_fmcadc5_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_fmcadc5_cpack]
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {256}] $axi_fmcadc5_cpack
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_fmcadc5_cpack
fmcadc5: 2014.4 updates
2015-03-23 14:00:20 +00:00
# connections (gt)
Merge branch 'hdl_2014_r2' into dev Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.v
2014-12-08 16:32:13 +00:00
fmcadc5- gt/ip updates
2015-10-15 20:05:15 +00:00
ad_connect util_fmcadc5_0_gt/cpll_ref_clk rx_ref_clk_0
ad_connect util_fmcadc5_1_gt/cpll_ref_clk rx_ref_clk_1
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
ad_connect axi_fmcadc5_0_gt/gt_qpll_0 util_fmcadc5_0_gt/gt_qpll_0
ad_connect axi_fmcadc5_0_gt/gt_qpll_1 util_fmcadc5_0_gt/gt_qpll_1
ad_connect axi_fmcadc5_0_gt/gt_pll_0 util_fmcadc5_0_gt/gt_pll_0
ad_connect axi_fmcadc5_0_gt/gt_pll_1 util_fmcadc5_0_gt/gt_pll_1
ad_connect axi_fmcadc5_0_gt/gt_pll_2 util_fmcadc5_0_gt/gt_pll_2
ad_connect axi_fmcadc5_0_gt/gt_pll_3 util_fmcadc5_0_gt/gt_pll_3
ad_connect axi_fmcadc5_0_gt/gt_pll_4 util_fmcadc5_0_gt/gt_pll_4
ad_connect axi_fmcadc5_0_gt/gt_pll_5 util_fmcadc5_0_gt/gt_pll_5
ad_connect axi_fmcadc5_0_gt/gt_pll_6 util_fmcadc5_0_gt/gt_pll_6
ad_connect axi_fmcadc5_0_gt/gt_pll_7 util_fmcadc5_0_gt/gt_pll_7
ad_connect axi_fmcadc5_1_gt/gt_qpll_0 util_fmcadc5_1_gt/gt_qpll_0
ad_connect axi_fmcadc5_1_gt/gt_qpll_1 util_fmcadc5_1_gt/gt_qpll_1
ad_connect axi_fmcadc5_1_gt/gt_pll_0 util_fmcadc5_1_gt/gt_pll_0
ad_connect axi_fmcadc5_1_gt/gt_pll_1 util_fmcadc5_1_gt/gt_pll_1
ad_connect axi_fmcadc5_1_gt/gt_pll_2 util_fmcadc5_1_gt/gt_pll_2
ad_connect axi_fmcadc5_1_gt/gt_pll_3 util_fmcadc5_1_gt/gt_pll_3
ad_connect axi_fmcadc5_1_gt/gt_pll_4 util_fmcadc5_1_gt/gt_pll_4
ad_connect axi_fmcadc5_1_gt/gt_pll_5 util_fmcadc5_1_gt/gt_pll_5
ad_connect axi_fmcadc5_1_gt/gt_pll_6 util_fmcadc5_1_gt/gt_pll_6
ad_connect axi_fmcadc5_1_gt/gt_pll_7 util_fmcadc5_1_gt/gt_pll_7
ad_connect axi_fmcadc5_0_gt/gt_rx_0 util_fmcadc5_0_gt/gt_rx_0
ad_connect axi_fmcadc5_0_gt/gt_rx_1 util_fmcadc5_0_gt/gt_rx_1
ad_connect axi_fmcadc5_0_gt/gt_rx_2 util_fmcadc5_0_gt/gt_rx_2
ad_connect axi_fmcadc5_0_gt/gt_rx_3 util_fmcadc5_0_gt/gt_rx_3
ad_connect axi_fmcadc5_0_gt/gt_rx_4 util_fmcadc5_0_gt/gt_rx_4
ad_connect axi_fmcadc5_0_gt/gt_rx_5 util_fmcadc5_0_gt/gt_rx_5
ad_connect axi_fmcadc5_0_gt/gt_rx_6 util_fmcadc5_0_gt/gt_rx_6
ad_connect axi_fmcadc5_0_gt/gt_rx_7 util_fmcadc5_0_gt/gt_rx_7
ad_connect axi_fmcadc5_1_gt/gt_rx_0 util_fmcadc5_1_gt/gt_rx_0
ad_connect axi_fmcadc5_1_gt/gt_rx_1 util_fmcadc5_1_gt/gt_rx_1
ad_connect axi_fmcadc5_1_gt/gt_rx_2 util_fmcadc5_1_gt/gt_rx_2
ad_connect axi_fmcadc5_1_gt/gt_rx_3 util_fmcadc5_1_gt/gt_rx_3
ad_connect axi_fmcadc5_1_gt/gt_rx_4 util_fmcadc5_1_gt/gt_rx_4
ad_connect axi_fmcadc5_1_gt/gt_rx_5 util_fmcadc5_1_gt/gt_rx_5
ad_connect axi_fmcadc5_1_gt/gt_rx_6 util_fmcadc5_1_gt/gt_rx_6
ad_connect axi_fmcadc5_1_gt/gt_rx_7 util_fmcadc5_1_gt/gt_rx_7
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_0 axi_ad9625_0_jesd/gt0_rx
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_1 axi_ad9625_0_jesd/gt1_rx
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_2 axi_ad9625_0_jesd/gt2_rx
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_3 axi_ad9625_0_jesd/gt3_rx
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_4 axi_ad9625_0_jesd/gt4_rx
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_5 axi_ad9625_0_jesd/gt5_rx
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_6 axi_ad9625_0_jesd/gt6_rx
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_7 axi_ad9625_0_jesd/gt7_rx
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_0 axi_ad9625_1_jesd/gt0_rx
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_1 axi_ad9625_1_jesd/gt1_rx
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_2 axi_ad9625_1_jesd/gt2_rx
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_3 axi_ad9625_1_jesd/gt3_rx
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_4 axi_ad9625_1_jesd/gt4_rx
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_5 axi_ad9625_1_jesd/gt5_rx
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_6 axi_ad9625_1_jesd/gt6_rx
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_7 axi_ad9625_1_jesd/gt7_rx
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_0 axi_ad9625_0_jesd/rxencommaalign_out
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_1 axi_ad9625_0_jesd/rxencommaalign_out
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_2 axi_ad9625_0_jesd/rxencommaalign_out
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_3 axi_ad9625_0_jesd/rxencommaalign_out
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_4 axi_ad9625_0_jesd/rxencommaalign_out
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_5 axi_ad9625_0_jesd/rxencommaalign_out
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_6 axi_ad9625_0_jesd/rxencommaalign_out
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_7 axi_ad9625_0_jesd/rxencommaalign_out
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_0 axi_ad9625_1_jesd/rxencommaalign_out
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_1 axi_ad9625_1_jesd/rxencommaalign_out
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_2 axi_ad9625_1_jesd/rxencommaalign_out
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_3 axi_ad9625_1_jesd/rxencommaalign_out
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_4 axi_ad9625_1_jesd/rxencommaalign_out
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_5 axi_ad9625_1_jesd/rxencommaalign_out
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_6 axi_ad9625_1_jesd/rxencommaalign_out
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_7 axi_ad9625_1_jesd/rxencommaalign_out
Merge branch 'hdl_2014_r2' into dev Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.v
2014-12-08 16:32:13 +00:00
fmcadc5: 2014.4 updates
2015-03-23 14:00:20 +00:00
# connections (adc)
Merge branch 'hdl_2014_r2' into dev Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.v
2014-12-08 16:32:13 +00:00
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
ad_connect util_fmcadc5_0_gt/rx_p rx_data_0_p
ad_connect util_fmcadc5_0_gt/rx_n rx_data_0_n
fmcadc5- gt/ip updates
2015-10-15 20:05:15 +00:00
ad_connect util_fmcadc5_0_gt/rx_sysref GND
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
ad_connect util_fmcadc5_0_gt/rx_sync rx_sync_0
fmcadc5- gt/ip updates
2015-10-15 20:05:15 +00:00
ad_connect util_fmcadc5_1_gt/rx_p rx_data_1_p
ad_connect util_fmcadc5_1_gt/rx_n rx_data_1_n
ad_connect util_fmcadc5_1_gt/rx_sysref GND
ad_connect util_fmcadc5_1_gt/rx_sync rx_sync_1
fmcadc5- fix core connections
2015-10-29 20:47:56 +00:00
ad_connect util_fmcadc5_0_gt/rx_ip_sysref rx_sysref
fmcadc5: add programmable io delay
2015-11-02 17:10:08 +00:00
ad_connect util_fmcadc5_0_gt/rx_out_clk rx_clk
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
ad_connect util_fmcadc5_0_gt/rx_out_clk util_fmcadc5_0_gt/rx_clk
ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_0_jesd/rx_core_clk
ad_connect util_fmcadc5_0_gt/rx_ip_rst axi_ad9625_0_jesd/rx_reset
ad_connect util_fmcadc5_0_gt/rx_ip_rst_done axi_ad9625_0_jesd/rx_reset_done
ad_connect util_fmcadc5_0_gt/rx_ip_sysref axi_ad9625_0_jesd/rx_sysref
ad_connect util_fmcadc5_0_gt/rx_ip_sync axi_ad9625_0_jesd/rx_sync
ad_connect util_fmcadc5_0_gt/rx_ip_sof axi_ad9625_0_jesd/rx_start_of_frame
ad_connect util_fmcadc5_0_gt/rx_ip_data axi_ad9625_0_jesd/rx_tdata
fmcadc5- gt/ip updates
2015-10-15 20:05:15 +00:00
ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_0_core/rx_clk
ad_connect util_fmcadc5_0_gt/rx_data axi_ad9625_0_core/rx_data
ad_connect util_fmcadc5_0_gt/rx_out_clk util_fmcadc5_1_gt/rx_clk
ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_1_jesd/rx_core_clk
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
ad_connect util_fmcadc5_1_gt/rx_ip_rst axi_ad9625_1_jesd/rx_reset
ad_connect util_fmcadc5_1_gt/rx_ip_rst_done axi_ad9625_1_jesd/rx_reset_done
fmcadc5- fix core connections
2015-10-29 20:47:56 +00:00
ad_connect util_fmcadc5_0_gt/rx_ip_sysref axi_ad9625_1_jesd/rx_sysref
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
ad_connect util_fmcadc5_1_gt/rx_ip_sync axi_ad9625_1_jesd/rx_sync
ad_connect util_fmcadc5_1_gt/rx_ip_sof axi_ad9625_1_jesd/rx_start_of_frame
ad_connect util_fmcadc5_1_gt/rx_ip_data axi_ad9625_1_jesd/rx_tdata
fmcadc5- gt/ip updates
2015-10-15 20:05:15 +00:00
ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_1_core/rx_clk
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
ad_connect util_fmcadc5_1_gt/rx_data axi_ad9625_1_core/rx_data
fmcadc5- gt/ip updates
2015-10-15 20:05:15 +00:00
ad_connect util_fmcadc5_0_gt/rx_out_clk axi_fmcadc5_cpack/adc_clk
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
ad_connect util_fmcadc5_0_gt/rx_rst axi_fmcadc5_cpack/adc_rst
fmcadc5- fix core connections
2015-10-29 20:47:56 +00:00
ad_connect axi_ad9625_0_core/adc_raddr_out axi_ad9625_0_core/adc_raddr_in
ad_connect axi_ad9625_0_core/adc_raddr_out axi_ad9625_1_core/adc_raddr_in
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
ad_connect axi_ad9625_0_core/adc_enable axi_fmcadc5_cpack/adc_enable_0
ad_connect axi_ad9625_0_core/adc_valid axi_fmcadc5_cpack/adc_valid_0
ad_connect axi_ad9625_0_core/adc_data axi_fmcadc5_cpack/adc_data_0
ad_connect axi_ad9625_1_core/adc_enable axi_fmcadc5_cpack/adc_enable_1
ad_connect axi_ad9625_1_core/adc_valid axi_fmcadc5_cpack/adc_valid_1
ad_connect axi_ad9625_1_core/adc_data axi_fmcadc5_cpack/adc_data_1
fmcadc5- gt/ip updates
2015-10-15 20:05:15 +00:00
ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_fifo/adc_clk
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
ad_connect util_fmcadc5_0_gt/rx_rst axi_ad9625_fifo/adc_rst
ad_connect axi_fmcadc5_cpack/adc_valid axi_ad9625_fifo/adc_wr
ad_connect axi_fmcadc5_cpack/adc_data axi_ad9625_fifo/adc_wdata
fmcadc5: 2014.4 updates
2015-03-23 14:00:20 +00:00
ad_connect axi_ad9625_0_core/adc_dovf axi_ad9625_fifo/adc_wovf
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk
fmcadc5- gt/ip updates
2015-10-15 20:05:15 +00:00
ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk
ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
fmcadc5: 2014.4 updates
2015-03-23 14:00:20 +00:00
ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid
ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data
fmcadc5- gt/ip updates
2015-10-15 20:05:15 +00:00
ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready
fmcadc5: 2014.4 updates
2015-03-23 14:00:20 +00:00
ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
Merge branch 'hdl_2014_r2' into dev Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.v
2014-12-08 16:32:13 +00:00
fmcadc5: 2014.4 updates
2015-03-23 14:00:20 +00:00
# interconnect (cpu)
Merge branch 'hdl_2014_r2' into dev Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.v
2014-12-08 16:32:13 +00:00
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
ad_cpu_interconnect 0x44a60000 axi_fmcadc5_0_gt
ad_cpu_interconnect 0x44b60000 axi_fmcadc5_1_gt
fmcadc5: 2014.4 updates
2015-03-23 14:00:20 +00:00
ad_cpu_interconnect 0x44a10000 axi_ad9625_0_core
ad_cpu_interconnect 0x44b10000 axi_ad9625_1_core
ad_cpu_interconnect 0x44a91000 axi_ad9625_0_jesd
ad_cpu_interconnect 0x44b91000 axi_ad9625_1_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9625_dma
Merge branch 'hdl_2014_r2' into dev Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.v
2014-12-08 16:32:13 +00:00
fmcadc5: 2014.4 updates
2015-03-23 14:00:20 +00:00
# interconnect (gt/adc)
Merge branch 'hdl_2014_r2' into dev Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.v
2014-12-08 16:32:13 +00:00
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
ad_mem_hp0_interconnect sys_cpu_clk axi_fmcadc5_0_gt/m_axi
ad_mem_hp0_interconnect sys_cpu_clk axi_fmcadc5_1_gt/m_axi
fmcadc5: 2014.4 updates
2015-03-23 14:00:20 +00:00
ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_dma/m_dest_axi
Merge branch 'hdl_2014_r2' into dev Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.v
2014-12-08 16:32:13 +00:00
fmcadc5: 2014.4 updates
2015-03-23 14:00:20 +00:00
# interrupts
Merge branch 'hdl_2014_r2' into dev Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.v
2014-12-08 16:32:13 +00:00
fmcadc5: Update project + Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interface
2015-09-25 15:05:03 +00:00
ad_cpu_interrupt ps-13 mb-12 axi_ad9625_dma/irq
Merge branch 'hdl_2014_r2' into dev Conflicts: projects/fmcadc5/common/fmcadc5_bd.tcl projects/motcon1_fmc/common/motcon1_fmc_bd.tcl projects/motcon1_fmc/zed/system_constr.xdc projects/motcon1_fmc/zed/system_top.v
2014-12-08 16:32:13 +00:00
fmcadc5- regulators need a switching ref clock?
2015-10-15 14:43:09 +00:00
# sync
create_bd_port -dir O up_clk
create_bd_port -dir O up_rstn
fmcadc5: add programmable io delay
2015-11-02 17:10:08 +00:00
create_bd_port -dir O delay_clk
create_bd_port -dir O delay_rst
fmcadc5- regulators need a switching ref clock?
2015-10-15 14:43:09 +00:00
ad_connect sys_cpu_clk up_clk
ad_connect sys_cpu_resetn up_rstn
fmcadc5: add programmable io delay
2015-11-02 17:10:08 +00:00
ad_connect sys_200m_clk delay_clk
ad_connect sys_cpu_reset delay_rst
fmcadc5- regulators need a switching ref clock?
2015-10-15 14:43:09 +00:00