2015-07-01 10:52:00 +00:00
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9361 (
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// physical interface (receive)
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rx_clk_in_p,
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rx_clk_in_n,
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rx_frame_in_p,
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rx_frame_in_n,
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rx_data_in_p,
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rx_data_in_n,
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// physical interface (transmit)
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tx_clk_out_p,
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tx_clk_out_n,
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tx_frame_out_p,
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tx_frame_out_n,
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tx_data_out_p,
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tx_data_out_n,
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// transmit master/slave
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dac_sync_in,
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dac_sync_out,
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// delay clock
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delay_clk,
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// master interface
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l_clk,
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clk,
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rst,
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// dma interface
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adc_enable_i0,
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adc_valid_i0,
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adc_data_i0,
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adc_enable_q0,
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adc_valid_q0,
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adc_data_q0,
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adc_enable_i1,
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adc_valid_i1,
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adc_data_i1,
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adc_enable_q1,
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adc_valid_q1,
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adc_data_q1,
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adc_dovf,
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adc_dunf,
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adc_r1_mode,
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dac_enable_i0,
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dac_valid_i0,
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dac_data_i0,
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dac_enable_q0,
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dac_valid_q0,
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dac_data_q0,
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dac_enable_i1,
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dac_valid_i1,
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dac_data_i1,
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dac_enable_q1,
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dac_valid_q1,
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dac_data_q1,
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dac_dovf,
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dac_dunf,
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dac_r1_mode,
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tdd_enable,
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enable,
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txnrx,
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// axi interface
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awprot,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arprot,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rdata,
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s_axi_rresp,
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s_axi_rready,
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// gpio
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up_dac_gpio_in,
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up_dac_gpio_out,
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up_adc_gpio_in,
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up_adc_gpio_out,
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// chipscope signals
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tdd_dbg);
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// parameters
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parameter PCORE_ID = 0;
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parameter PCORE_DEVICE_TYPE = 0;
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parameter PCORE_DAC_IODELAY_ENABLE = 0;
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parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
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parameter PCORE_DAC_DP_DISABLE = 0;
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parameter PCORE_ADC_DP_DISABLE = 0;
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// physical interface (receive)
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input rx_clk_in_p;
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input rx_clk_in_n;
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input rx_frame_in_p;
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input rx_frame_in_n;
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input [ 5:0] rx_data_in_p;
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input [ 5:0] rx_data_in_n;
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// physical interface (transmit)
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output tx_clk_out_p;
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output tx_clk_out_n;
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output tx_frame_out_p;
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output tx_frame_out_n;
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output [ 5:0] tx_data_out_p;
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output [ 5:0] tx_data_out_n;
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// master/slave
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input dac_sync_in;
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output dac_sync_out;
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// delay clock
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input delay_clk;
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// master interface
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output l_clk;
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input clk;
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output rst;
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// dma interface
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output adc_enable_i0;
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output adc_valid_i0;
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output [15:0] adc_data_i0;
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output adc_enable_q0;
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output adc_valid_q0;
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output [15:0] adc_data_q0;
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output adc_enable_i1;
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output adc_valid_i1;
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output [15:0] adc_data_i1;
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output adc_enable_q1;
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output adc_valid_q1;
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output [15:0] adc_data_q1;
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input adc_dovf;
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input adc_dunf;
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output adc_r1_mode;
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output dac_enable_i0;
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output dac_valid_i0;
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input [15:0] dac_data_i0;
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output dac_enable_q0;
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output dac_valid_q0;
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input [15:0] dac_data_q0;
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output dac_enable_i1;
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output dac_valid_i1;
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input [15:0] dac_data_i1;
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output dac_enable_q1;
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output dac_valid_q1;
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input [15:0] dac_data_q1;
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input dac_dovf;
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input dac_dunf;
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output dac_r1_mode;
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output tdd_enable;
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output enable;
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output txnrx;
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// axi interface
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [31:0] s_axi_awaddr;
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input [ 2:0] s_axi_awprot;
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output s_axi_awready;
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input s_axi_wvalid;
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input [31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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input s_axi_bready;
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input s_axi_arvalid;
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input [31:0] s_axi_araddr;
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input [ 2:0] s_axi_arprot;
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output s_axi_arready;
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output s_axi_rvalid;
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output [31:0] s_axi_rdata;
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output [ 1:0] s_axi_rresp;
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input s_axi_rready;
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// gpio
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input [31:0] up_dac_gpio_in;
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output [31:0] up_dac_gpio_out;
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input [31:0] up_adc_gpio_in;
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output [31:0] up_adc_gpio_out;
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// chipscope signals
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output [34:0] tdd_dbg;
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// internal registers
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reg up_wack = 'd0;
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reg up_rack = 'd0;
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reg [31:0] up_rdata = 'd0;
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// internal clocks and resets
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wire up_clk;
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wire up_rstn;
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wire delay_rst;
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// internal signals
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wire adc_ddr_edgesel;
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wire adc_valid_s;
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wire [47:0] adc_data_s;
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wire adc_status_s;
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wire dac_valid_s;
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wire [47:0] dac_data_s;
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wire [ 6:0] up_adc_dld_s;
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wire [34:0] up_adc_dwdata_s;
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wire [34:0] up_adc_drdata_s;
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wire [ 7:0] up_dac_dld_s;
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wire [39:0] up_dac_dwdata_s;
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wire [39:0] up_dac_drdata_s;
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wire delay_locked_s;
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_wack_rx_s;
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wire up_wack_tx_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_rx_s;
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wire up_rack_rx_s;
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wire [31:0] up_rdata_tx_s;
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wire up_rack_tx_s;
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wire up_wack_tdd_s;
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wire up_rack_tdd_s;
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wire [31:0] up_rdata_tdd_s;
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wire tdd_tx_dp_en_s;
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wire tdd_rx_vco_en_s;
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wire tdd_tx_vco_en_s;
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wire tdd_rx_rf_en_s;
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wire tdd_tx_rf_en_s;
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wire [ 7:0] tdd_status_s;
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wire dac_valid_i0_s;
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wire dac_valid_q0_s;
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wire dac_valid_i1_s;
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wire dac_valid_q1_s;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_wack <= up_wack_rx_s | up_wack_tx_s | up_wack_tdd_s;
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up_rack <= up_rack_rx_s | up_rack_tx_s | up_rack_tdd_s;
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|
|
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|
up_rdata <= up_rdata_rx_s | up_rdata_tx_s | up_rdata_tdd_s;
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|
|
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|
end
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|
end
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|
|
|
// device interface
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axi_ad9361_dev_if #(
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.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
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.PCORE_DAC_IODELAY_ENABLE (PCORE_DAC_IODELAY_ENABLE),
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.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
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i_dev_if (
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.rx_clk_in_p (rx_clk_in_p),
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.rx_clk_in_n (rx_clk_in_n),
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.rx_frame_in_p (rx_frame_in_p),
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|
.rx_frame_in_n (rx_frame_in_n),
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.rx_data_in_p (rx_data_in_p),
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.rx_data_in_n (rx_data_in_n),
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.tx_clk_out_p (tx_clk_out_p),
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.tx_clk_out_n (tx_clk_out_n),
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.tx_frame_out_p (tx_frame_out_p),
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.tx_frame_out_n (tx_frame_out_n),
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|
.tx_data_out_p (tx_data_out_p),
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.tx_data_out_n (tx_data_out_n),
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.rst (rst),
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.l_clk (l_clk),
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.clk (clk),
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.adc_valid (adc_valid_s),
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.adc_data (adc_data_s),
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.adc_status (adc_status_s),
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.adc_r1_mode (adc_r1_mode),
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.adc_ddr_edgesel (adc_ddr_edgesel),
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|
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.dac_valid (dac_valid_s),
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.dac_data (dac_data_s),
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.dac_r1_mode (dac_r1_mode),
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|
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.up_clk (up_clk),
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|
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.up_adc_dld (up_adc_dld_s),
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|
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|
.up_adc_dwdata (up_adc_dwdata_s),
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|
.up_adc_drdata (up_adc_drdata_s),
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|
|
.up_dac_dld (up_dac_dld_s),
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|
|
.up_dac_dwdata (up_dac_dwdata_s),
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|
|
.up_dac_drdata (up_dac_drdata_s),
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|
|
.delay_clk (delay_clk),
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|
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.delay_rst (delay_rst),
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|
|
.delay_locked (delay_locked_s));
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// TDD interface
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axi_ad9361_tdd_if #(.MODE_OF_ENABLE(1)) i_tdd_if(
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|
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.clk(clk),
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|
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.rst(rst),
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|
|
.tdd_rx_vco_en(tdd_rx_vco_en_s),
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|
|
|
.tdd_tx_vco_en(tdd_tx_vco_en_s),
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|
|
|
|
.tdd_rx_rf_en(tdd_rx_rf_en_s),
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|
|
|
|
.tdd_tx_rf_en(tdd_tx_rf_en_s),
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|
|
|
|
.ad9361_txnrx(txnrx),
|
|
|
|
|
.ad9361_enable(enable),
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|
|
|
|
.ad9361_tdd_status(tdd_status_s)
|
|
|
|
|
);
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|
|
// TDD control
|
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|
|
axi_ad9361_tdd i_tdd(
|
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|
|
|
.clk(clk),
|
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|
|
|
.rst(rst),
|
|
|
|
|
.tdd_rx_vco_en(tdd_rx_vco_en_s),
|
|
|
|
|
.tdd_tx_vco_en(tdd_tx_vco_en_s),
|
|
|
|
|
.tdd_rx_rf_en(tdd_rx_rf_en_s),
|
|
|
|
|
.tdd_tx_rf_en(tdd_tx_rf_en_s),
|
|
|
|
|
.tdd_enable (tdd_enable),
|
|
|
|
|
.tdd_status(tdd_status_s),
|
|
|
|
|
.tx_valid_i0(dac_valid_i0_s),
|
|
|
|
|
.tx_valid_q0(dac_valid_q0_s),
|
|
|
|
|
.tx_valid_i1(dac_valid_i1_s),
|
|
|
|
|
.tx_valid_q1(dac_valid_q1_s),
|
|
|
|
|
.tdd_tx_valid_i0(dac_valid_i0),
|
|
|
|
|
.tdd_tx_valid_q0(dac_valid_q0),
|
|
|
|
|
.tdd_tx_valid_i1(dac_valid_i1),
|
|
|
|
|
.tdd_tx_valid_q1(dac_valid_q1),
|
|
|
|
|
.up_rstn(up_rstn),
|
|
|
|
|
.up_clk(up_clk),
|
|
|
|
|
.up_wreq(up_wreq_s),
|
|
|
|
|
.up_waddr(up_waddr_s),
|
|
|
|
|
.up_wdata(up_wdata_s),
|
|
|
|
|
.up_wack(up_wack_tdd_s),
|
|
|
|
|
.up_rreq(up_rreq_s),
|
|
|
|
|
.up_raddr(up_raddr_s),
|
|
|
|
|
.up_rdata(up_rdata_tdd_s),
|
|
|
|
|
.up_rack(up_rack_tdd_s),
|
|
|
|
|
.tdd_dbg(tdd_dbg)
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// receive
|
|
|
|
|
|
|
|
|
|
axi_ad9361_rx #(
|
|
|
|
|
.PCORE_ID (PCORE_ID),
|
|
|
|
|
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
|
|
|
|
|
i_rx (
|
|
|
|
|
.adc_rst (rst),
|
|
|
|
|
.adc_clk (clk),
|
|
|
|
|
.adc_valid (adc_valid_s),
|
|
|
|
|
.adc_data (adc_data_s),
|
|
|
|
|
.adc_status (adc_status_s),
|
|
|
|
|
.adc_r1_mode (adc_r1_mode),
|
|
|
|
|
.adc_ddr_edgesel (adc_ddr_edgesel),
|
|
|
|
|
.dac_data (dac_data_s),
|
|
|
|
|
.up_dld (up_adc_dld_s),
|
|
|
|
|
.up_dwdata (up_adc_dwdata_s),
|
|
|
|
|
.up_drdata (up_adc_drdata_s),
|
|
|
|
|
.delay_clk (delay_clk),
|
|
|
|
|
.delay_rst (delay_rst),
|
|
|
|
|
.delay_locked (delay_locked_s),
|
|
|
|
|
.adc_enable_i0 (adc_enable_i0),
|
|
|
|
|
.adc_valid_i0 (adc_valid_i0),
|
|
|
|
|
.adc_data_i0 (adc_data_i0),
|
|
|
|
|
.adc_enable_q0 (adc_enable_q0),
|
|
|
|
|
.adc_valid_q0 (adc_valid_q0),
|
|
|
|
|
.adc_data_q0 (adc_data_q0),
|
|
|
|
|
.adc_enable_i1 (adc_enable_i1),
|
|
|
|
|
.adc_valid_i1 (adc_valid_i1),
|
|
|
|
|
.adc_data_i1 (adc_data_i1),
|
|
|
|
|
.adc_enable_q1 (adc_enable_q1),
|
|
|
|
|
.adc_valid_q1 (adc_valid_q1),
|
|
|
|
|
.adc_data_q1 (adc_data_q1),
|
|
|
|
|
.adc_dovf (adc_dovf),
|
|
|
|
|
.adc_dunf (adc_dunf),
|
|
|
|
|
.up_adc_gpio_in (up_adc_gpio_in),
|
|
|
|
|
.up_adc_gpio_out (up_adc_gpio_out),
|
|
|
|
|
.up_rstn (up_rstn),
|
|
|
|
|
.up_clk (up_clk),
|
|
|
|
|
.up_wreq (up_wreq_s),
|
|
|
|
|
.up_waddr (up_waddr_s),
|
|
|
|
|
.up_wdata (up_wdata_s),
|
|
|
|
|
.up_wack (up_wack_rx_s),
|
|
|
|
|
.up_rreq (up_rreq_s),
|
|
|
|
|
.up_raddr (up_raddr_s),
|
|
|
|
|
.up_rdata (up_rdata_rx_s),
|
|
|
|
|
.up_rack (up_rack_rx_s));
|
|
|
|
|
|
|
|
|
|
// transmit
|
|
|
|
|
|
|
|
|
|
axi_ad9361_tx #(
|
|
|
|
|
.PCORE_ID (PCORE_ID),
|
|
|
|
|
.DP_DISABLE (PCORE_DAC_DP_DISABLE))
|
|
|
|
|
i_tx (
|
|
|
|
|
.dac_clk (clk),
|
|
|
|
|
.dac_valid (dac_valid_s),
|
|
|
|
|
.dac_data (dac_data_s),
|
|
|
|
|
.dac_r1_mode (dac_r1_mode),
|
|
|
|
|
.adc_data (adc_data_s),
|
|
|
|
|
.up_dld (up_dac_dld_s),
|
|
|
|
|
.up_dwdata (up_dac_dwdata_s),
|
|
|
|
|
.up_drdata (up_dac_drdata_s),
|
|
|
|
|
.delay_clk (delay_clk),
|
|
|
|
|
.delay_rst (),
|
|
|
|
|
.delay_locked (delay_locked_s),
|
|
|
|
|
.dac_sync_in (dac_sync_in),
|
|
|
|
|
.dac_sync_out (dac_sync_out),
|
|
|
|
|
.dac_enable_i0 (dac_enable_i0),
|
|
|
|
|
.dac_valid_i0 (dac_valid_i0_s),
|
|
|
|
|
.dac_data_i0 (dac_data_i0),
|
|
|
|
|
.dac_enable_q0 (dac_enable_q0),
|
|
|
|
|
.dac_valid_q0 (dac_valid_q0_s),
|
|
|
|
|
.dac_data_q0 (dac_data_q0),
|
|
|
|
|
.dac_enable_i1 (dac_enable_i1),
|
|
|
|
|
.dac_valid_i1 (dac_valid_i1_s),
|
|
|
|
|
.dac_data_i1 (dac_data_i1),
|
|
|
|
|
.dac_enable_q1 (dac_enable_q1),
|
|
|
|
|
.dac_valid_q1 (dac_valid_q1_s),
|
|
|
|
|
.dac_data_q1 (dac_data_q1),
|
|
|
|
|
.dac_dovf(dac_dovf),
|
|
|
|
|
.dac_dunf(dac_dunf),
|
|
|
|
|
.up_dac_gpio_in (up_dac_gpio_in),
|
|
|
|
|
.up_dac_gpio_out (up_dac_gpio_out),
|
|
|
|
|
.up_rstn (up_rstn),
|
|
|
|
|
.up_clk (up_clk),
|
|
|
|
|
.up_wreq (up_wreq_s),
|
|
|
|
|
.up_waddr (up_waddr_s),
|
|
|
|
|
.up_wdata (up_wdata_s),
|
|
|
|
|
.up_wack (up_wack_tx_s),
|
|
|
|
|
.up_rreq (up_rreq_s),
|
|
|
|
|
.up_raddr (up_raddr_s),
|
|
|
|
|
.up_rdata (up_rdata_tx_s),
|
|
|
|
|
.up_rack (up_rack_tx_s));
|
|
|
|
|
|
|
|
|
|
// axi interface
|
|
|
|
|
|
|
|
|
|
up_axi i_up_axi (
|
|
|
|
|
.up_rstn (up_rstn),
|
|
|
|
|
.up_clk (up_clk),
|
|
|
|
|
.up_axi_awvalid (s_axi_awvalid),
|
|
|
|
|
.up_axi_awaddr (s_axi_awaddr),
|
|
|
|
|
.up_axi_awready (s_axi_awready),
|
|
|
|
|
.up_axi_wvalid (s_axi_wvalid),
|
|
|
|
|
.up_axi_wdata (s_axi_wdata),
|
|
|
|
|
.up_axi_wstrb (s_axi_wstrb),
|
|
|
|
|
.up_axi_wready (s_axi_wready),
|
|
|
|
|
.up_axi_bvalid (s_axi_bvalid),
|
|
|
|
|
.up_axi_bresp (s_axi_bresp),
|
|
|
|
|
.up_axi_bready (s_axi_bready),
|
|
|
|
|
.up_axi_arvalid (s_axi_arvalid),
|
|
|
|
|
.up_axi_araddr (s_axi_araddr),
|
|
|
|
|
.up_axi_arready (s_axi_arready),
|
|
|
|
|
.up_axi_rvalid (s_axi_rvalid),
|
|
|
|
|
.up_axi_rresp (s_axi_rresp),
|
|
|
|
|
.up_axi_rdata (s_axi_rdata),
|
|
|
|
|
.up_axi_rready (s_axi_rready),
|
|
|
|
|
.up_wreq (up_wreq_s),
|
|
|
|
|
.up_waddr (up_waddr_s),
|
|
|
|
|
.up_wdata (up_wdata_s),
|
|
|
|
|
.up_wack (up_wack),
|
|
|
|
|
.up_rreq (up_rreq_s),
|
|
|
|
|
.up_raddr (up_raddr_s),
|
|
|
|
|
.up_rdata (up_rdata),
|
|
|
|
|
.up_rack (up_rack));
|
|
|
|
|
|
|
|
|
|
endmodule
|
|
|
|
|
|
|
|
|
|
// ***************************************************************************
|
|
|
|
|
// ***************************************************************************
|
