pluto_hdl_adi/library/altera/common/ad_serdes_out.v

// ***************************************************************************
// ***************************************************************************
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// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8)

`timescale 1ps/1ps

module ad_serdes_out (

  // reset and clocks

  input                       rst,
  input                       clk,
  input                       div_clk,
  input                       loaden,

  // data interface

  input   [(DATA_WIDTH-1):0]  data_s0,
  input   [(DATA_WIDTH-1):0]  data_s1,
  input   [(DATA_WIDTH-1):0]  data_s2,
  input   [(DATA_WIDTH-1):0]  data_s3,
  input   [(DATA_WIDTH-1):0]  data_s4,
  input   [(DATA_WIDTH-1):0]  data_s5,
  input   [(DATA_WIDTH-1):0]  data_s6,
  input   [(DATA_WIDTH-1):0]  data_s7,
  output  [(DATA_WIDTH-1):0]  data_out_p,
  output  [(DATA_WIDTH-1):0]  data_out_n);

  // parameters

  parameter   DEVICE_TYPE = 0;
  parameter   DATA_WIDTH = 16;

  // internal signals

  wire    [(DATA_WIDTH-1):0]  data_out_s;
  wire    [ 7:0]              data_in_s[(DATA_WIDTH-1):0];

  // defaults

  assign data_out_n = 'd0;

  // instantiations

  genvar l_inst;
  generate
  for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data
  alt_serdes_out_core i_core (
    .clk_export (clk),
    .div_clk_export (div_clk),
    .loaden_export (loaden),
    .data_out_export (data_out_p[l_inst]),
    .data_s_export ({ data_s7[l_inst],
                      data_s6[l_inst],
                      data_s5[l_inst],
                      data_s4[l_inst],
                      data_s3[l_inst],
                      data_s2[l_inst],
                      data_s1[l_inst],
                      data_s0[l_inst]}));
  end
  endgenerate

endmodule

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