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pluto_hdl_adi/library/util_adcfifo/util_adcfifo_constr.xdc

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adcfifo: added
2015-04-07 19:43:02 +00:00
constraints: Update constraints Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.
2017-02-24 11:43:32 +00:00
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *adc_xfer_req_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dma_waddr_rel_t*}]
adcfifo: added
2015-04-07 19:43:02 +00:00
adc/dac- fifo constraints
2016-08-11 13:58:36 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *adc_waddr_rel_t_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dma_waddr_rel_t_m_reg[0]* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *adc_waddr_rel_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dma_waddr_rel_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *adc_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
adcfifo: added
2015-04-07 19:43:02 +00:00