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pluto_hdl_adi/projects/daq2/common/daq2_bd.tcl

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daq2: rebase conflicts
2014-10-22 20:39:17 +00:00
daq2: Convert to ADI JESD204 Convert the DAQ2 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-22 09:25:45 +00:00
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
set TX_NUM_OF_LANES 4 ; # L
set TX_NUM_OF_CONVERTERS 2 ; # M
set TX_SAMPLES_PER_FRAME 1 ; # S
set TX_SAMPLE_WIDTH 16 ; # N/NP
set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)]
daq2: update adcfifo/dacfifo
2019-01-22 13:19:37 +00:00
set dac_fifo_name axi_ad9144_fifo
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
set RX_NUM_OF_LANES 4 ; # L
set RX_NUM_OF_CONVERTERS 2 ; # M
set RX_SAMPLES_PER_FRAME 1 ; # S
set RX_SAMPLE_WIDTH 16 ; # N/NP
set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)]
set adc_fifo_name axi_ad9680_fifo
set adc_data_width [expr $RX_SAMPLE_WIDTH * $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_CHANNEL]
set adc_dma_data_width 64
daq2: update adcfifo/dacfifo
2019-01-22 13:19:37 +00:00
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# dac peripherals
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
ad_ip_instance axi_adxcvr axi_ad9144_xcvr
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_ip_parameter axi_ad9144_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
ad_ip_parameter axi_ad9144_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_ad9144_xcvr CONFIG.TX_OR_RX_N 1
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
adi_axi_jesd204_tx_create axi_ad9144_jesd $TX_NUM_OF_LANES
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
adi_tpl_jesd204_tx_create axi_ad9144_tpl $TX_NUM_OF_LANES \
$TX_NUM_OF_CONVERTERS \
$TX_SAMPLES_PER_FRAME \
$TX_SAMPLE_WIDTH \
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_ip_instance util_upack2 axi_ad9144_upack [list \
NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
]
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
ad_ip_instance axi_dmac axi_ad9144_dma
ad_ip_parameter axi_ad9144_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_ad9144_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_ad9144_dma CONFIG.ID 1
ad_ip_parameter axi_ad9144_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9144_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9144_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9144_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9144_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9144_dma CONFIG.DMA_DATA_WIDTH_SRC 128
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_ip_parameter axi_ad9144_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_data_width
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_data_width $dac_fifo_address_width
daq2: update adcfifo/dacfifo
2019-01-22 13:19:37 +00:00
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# adc peripherals
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
ad_ip_instance axi_adxcvr axi_ad9680_xcvr
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_ip_parameter axi_ad9680_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
ad_ip_parameter axi_ad9680_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9680_xcvr CONFIG.TX_OR_RX_N 0
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
adi_axi_jesd204_rx_create axi_ad9680_jesd $RX_NUM_OF_LANES
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
adi_tpl_jesd204_rx_create axi_ad9680_tpl $RX_NUM_OF_LANES \
$RX_NUM_OF_CONVERTERS \
$RX_SAMPLES_PER_FRAME \
$RX_SAMPLE_WIDTH \
ad_ip_instance util_cpack2 axi_ad9680_cpack [list \
NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
]
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
ad_ip_instance axi_dmac axi_ad9680_dma
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad9680_dma CONFIG.ID 0
ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST 0
daq2/fmcadc4/daq3: Disable the transfer start sync on the ADC DMA Explicitly disable the "Transfer Start Synchronisation Support" since the sync lines are not connected in this project. If the sync input line (s_axi_user[0] or fifo_wr_sync) are not connected, Vivado 2017.4.1 no longer connects them to the defaultValue defined in the axi_dmac ip (1). Instead he uses the defaulValue field defined in the interface definition which in case of both interfaces is 0;
2018-02-28 13:37:40 +00:00
ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 0
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
daq2: update adcfifo/dacfifo
2019-01-22 13:19:37 +00:00
ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
daq2- adxcvr version
2016-07-21 20:08:53 +00:00
# shared transceiver core
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
ad_ip_instance util_adxcvr util_daq2_xcvr
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_ip_parameter util_daq2_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter util_daq2_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
common/daq2: Fix typo
2018-08-23 11:06:53 +00:00
ad_ip_parameter util_daq2_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter util_daq2_xcvr CONFIG.QPLL_FBDIV_RATIO 1
ad_ip_parameter util_daq2_xcvr CONFIG.QPLL_FBDIV 0x30; # 20
ad_ip_parameter util_daq2_xcvr CONFIG.RX_OUT_DIV 1
ad_ip_parameter util_daq2_xcvr CONFIG.TX_OUT_DIV 1
ad_ip_parameter util_daq2_xcvr CONFIG.RX_DFE_LPM_CFG 0x0104
ad_ip_parameter util_daq2_xcvr CONFIG.RX_CDR_CFG 0x0B000023FF10400020
daq2- adxcvr version
2016-07-21 20:08:53 +00:00
block_design: Updates with new reset net variables
2019-05-30 06:43:44 +00:00
ad_connect $sys_cpu_resetn util_daq2_xcvr/up_rstn
ad_connect $sys_cpu_clk util_daq2_xcvr/up_clk
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
daq2: xcvr pll changes
2016-11-22 17:53:29 +00:00
# reference clocks & resets
create_bd_port -dir I tx_ref_clk_0
create_bd_port -dir I rx_ref_clk_0
projects/- xcvr updates
2016-11-22 21:23:05 +00:00
ad_xcvrpll tx_ref_clk_0 util_daq2_xcvr/qpll_ref_clk_*
ad_xcvrpll rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_*
ad_xcvrpll axi_ad9144_xcvr/up_pll_rst util_daq2_xcvr/up_qpll_rst_*
ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_*
daq2: xcvr pll changes
2016-11-22 17:53:29 +00:00
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# connections (dac)
daq2: Provide DAC lane map Provide the correct lane mapping for the DAQ2 DAC lanes which do not follow a 1-to-1 mapping between physical and logical lanes due to PCB layout constraints. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-29 11:36:27 +00:00
ad_xcvrcon util_daq2_xcvr axi_ad9144_xcvr axi_ad9144_jesd {0 2 3 1}
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_tpl/link_clk
ad_connect axi_ad9144_jesd/tx_data axi_ad9144_tpl/link
daq2: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:36:26 +00:00
ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_upack/clk
ad_connect axi_ad9144_jesd_rstgen/peripheral_reset axi_ad9144_upack/reset
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_connect axi_ad9144_tpl/dac_valid_0 axi_ad9144_upack/fifo_rd_en
for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
ad_connect axi_ad9144_tpl/dac_enable_$i axi_ad9144_upack/enable_$i
ad_connect axi_ad9144_tpl/dac_data_$i axi_ad9144_upack/fifo_rd_data_$i
daq2: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:36:26 +00:00
}
daq2- adxcvr version
2016-07-21 20:08:53 +00:00
ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_fifo/dac_clk
daq2_common: Fix the dac_rst for DAC FIFO
2017-03-07 14:13:46 +00:00
ad_connect axi_ad9144_jesd_rstgen/peripheral_reset axi_ad9144_fifo/dac_rst
daq2: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:36:26 +00:00
# TODO: Add streaming AXI interface for DAC FIFO
ad_connect axi_ad9144_upack/s_axis_valid VCC
ad_connect axi_ad9144_upack/s_axis_ready axi_ad9144_fifo/dac_valid
ad_connect axi_ad9144_upack/s_axis_data axi_ad9144_fifo/dac_data
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_connect axi_ad9144_tpl/dac_dunf axi_ad9144_fifo/dac_dunf
daq2: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:36:26 +00:00
block_design: Updates with new reset net variables
2019-05-30 06:43:44 +00:00
ad_connect $sys_cpu_clk axi_ad9144_fifo/dma_clk
ad_connect $sys_cpu_reset axi_ad9144_fifo/dma_rst
ad_connect $sys_cpu_clk axi_ad9144_dma/m_axis_aclk
ad_connect $sys_cpu_resetn axi_ad9144_dma/m_src_axi_aresetn
daq2: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:36:26 +00:00
daq2- gt changes
2015-08-17 18:11:41 +00:00
ad_connect axi_ad9144_fifo/dma_xfer_req axi_ad9144_dma/m_axis_xfer_req
ad_connect axi_ad9144_fifo/dma_ready axi_ad9144_dma/m_axis_ready
ad_connect axi_ad9144_fifo/dma_data axi_ad9144_dma/m_axis_data
ad_connect axi_ad9144_fifo/dma_valid axi_ad9144_dma/m_axis_valid
ad_connect axi_ad9144_fifo/dma_xfer_last axi_ad9144_dma/m_axis_last
daq2 : Integrate the DACFIFO into the supported projects. + All pack/unpack logic is made by the cpack and upack modules. + The DAC FIFO is integrated between the TX DMA and cpack. + All the top files are updated, all the projects compiled successfully.
2015-05-11 09:17:59 +00:00
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# connections (adc)
daq2- xcvr connect
2016-10-06 18:09:27 +00:00
ad_xcvrcon util_daq2_xcvr axi_ad9680_xcvr axi_ad9680_jesd
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_tpl/link_clk
ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_tpl/link_sof
ad_connect axi_ad9680_jesd/rx_data_tdata axi_ad9680_tpl/link_data
ad_connect axi_ad9680_jesd/rx_data_tvalid axi_ad9680_tpl/link_valid
daq2: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:36:26 +00:00
ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_cpack/clk
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/reset
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_connect axi_ad9680_tpl/adc_valid_0 axi_ad9680_cpack/fifo_wr_en
for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
ad_connect axi_ad9680_tpl/adc_enable_$i axi_ad9680_cpack/enable_$i
ad_connect axi_ad9680_tpl/adc_data_$i axi_ad9680_cpack/fifo_wr_data_$i
}
ad_connect axi_ad9680_tpl/adc_dovf axi_ad9680_cpack/fifo_wr_overflow
daq2: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:36:26 +00:00
daq2- adxcvr version
2016-07-21 20:08:53 +00:00
ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
daq2- xcvr connect
2016-10-06 18:09:27 +00:00
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
daq2: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:36:26 +00:00
ad_connect axi_ad9680_cpack/packed_fifo_wr_en axi_ad9680_fifo/adc_wr
ad_connect axi_ad9680_cpack/packed_fifo_wr_data axi_ad9680_fifo/adc_wdata
ad_connect axi_ad9680_cpack/packed_fifo_wr_overflow axi_ad9680_fifo/adc_wovf
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_connect $sys_cpu_clk axi_ad9680_fifo/dma_clk
ad_connect $sys_cpu_clk axi_ad9680_dma/s_axis_aclk
block_design: Updates with new reset net variables
2019-05-30 06:43:44 +00:00
ad_connect $sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
# interconnect (cpu)
daq2- adxcvr version
2016-07-21 20:08:53 +00:00
ad_cpu_interconnect 0x44A60000 axi_ad9144_xcvr
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_cpu_interconnect 0x44A04000 axi_ad9144_tpl
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9144_dma
daq2- spi+xcvr address conflict
2016-08-04 14:50:31 +00:00
ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_cpu_interconnect 0x44A10000 axi_ad9680_tpl
daq2: Convert to ADI JESD204 Convert the DAQ2 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-22 09:25:45 +00:00
ad_cpu_interconnect 0x44AA0000 axi_ad9680_jesd
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
# gt uses hp3, and 100MHz clock for both DRP and AXI4
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_mem_hp3_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect $sys_cpu_clk axi_ad9680_xcvr/m_axi
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# interconnect (mem/dac)
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9144_dma/m_src_axi
ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_cpu_clk axi_ad9680_dma/m_dest_axi
daq2: rebase conflicts
2014-10-22 20:39:17 +00:00
daq2: move intrs into ipi
2015-03-12 20:16:55 +00:00
# interrupts
daq2: rebase conflicts
2014-10-22 20:39:17 +00:00
Connect JESD204 interrupts Connect the ADI JESD204 link layer peripheral interrupt signals in all projects. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-02 08:24:37 +00:00
ad_cpu_interrupt ps-10 mb-15 axi_ad9144_jesd/irq
ad_cpu_interrupt ps-11 mb-14 axi_ad9680_jesd/irq
daq2 : Integrate the DACFIFO into the supported projects. + All pack/unpack logic is made by the cpack and upack modules. + The DAC FIFO is integrated between the TX DMA and cpack. + All the top files are updated, all the projects compiled successfully.
2015-05-11 09:17:59 +00:00
ad_cpu_interrupt ps-12 mb-13 axi_ad9144_dma/irq
ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
daq2: rebase conflicts
2014-10-22 20:39:17 +00:00
dacfifo- bypass port name change
2017-02-27 20:57:53 +00:00
ad_connect axi_ad9144_fifo/bypass GND
daq2/zc706: open ports
2015-06-10 18:25:58 +00:00