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pluto_hdl_adi/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl

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Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
###############################################################################
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
util_adxcvr- system verilog interfaces
2016-06-16 20:41:43 +00:00
Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
## AUTO GENERATED BY util_adxcvr.pl, DO NOT MODIFY!
scripts: Merge adi_env.tcl into a single file Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-07-12 11:06:15 +00:00
source ../../../scripts/adi_env.tcl
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2018-08-14 09:59:39 +00:00
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
util_adxcvr- system verilog interfaces
2016-06-16 20:41:43 +00:00
account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores
2022-03-18 21:10:26 +00:00
global VIVADO_IP_LIBRARY
util_adxcvr- system verilog interfaces
2016-06-16 20:41:43 +00:00
adi_ip_create util_adxcvr
adi_ip_files util_adxcvr [list \
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
"$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
xilinx/util_adxcvr: 204C link support for GTY4 Set channel parameters based on link mode (1 - 204b or 2 - 204c).
2021-04-19 13:57:55 +00:00
"$ad_hdl_dir/library/jesd204/jesd204_common/sync_header_align.v" \
util_adxcvr- add constraints file
2016-07-15 14:19:48 +00:00
"util_adxcvr_constr.xdc" \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
"util_adxcvr_xcm.v" \
"util_adxcvr_xch.v" \
library/xilinx/util_adxcvr: merge GTY and GTH prefixed parameter parameters with same names were duplicated with transceiver specific names due different default values. This does not scales very well. Use same name for the parameters as for other parameters and do the default value handling in the IP configuration layer.
2019-11-14 13:22:09 +00:00
"util_adxcvr.v" \
"bd/bd.tcl" ]
util_adxcvr- system verilog interfaces
2016-06-16 20:41:43 +00:00
adi_ip_properties_lite util_adxcvr
library/IPs: Auto-generate bd.tcl Update Remove all bd.tcl and respecting the previous commit, update *_ip.tcl to auto-generate bd.tcl for: - axi_ad5766/axi_ad5766_ip.tcl - axi_ad6676/axi_ad6676_ip.tcl - axi_ad9122/axi_ad9122_ip.tcl - axi_ad9144/axi_ad9144_ip.tcl - axi_ad9152/axi_ad9152_ip.tcl - axi_ad9162/axi_ad9162_ip.tcl - axi_ad9250/axi_ad9250_ip.tcl - axi_ad9265/axi_ad9265_ip.tcl - axi_ad9361/axi_ad9361_ip.tcl - axi_ad9371/axi_ad9371_ip.tcl - axi_ad9434/axi_ad9434_ip.tcl - axi_ad9467/axi_ad9467_ip.tcl - axi_ad9625/axi_ad9625_ip.tcl - axi_ad9671/axi_ad9671_ip.tcl - axi_ad9680/axi_ad9680_ip.tcl - axi_ad9684/axi_ad9684_ip.tcl - axi_ad9739a/axi_ad9739a_ip.tcl - axi_ad9963/axi_ad9963_ip.tcl - axi_adrv9009/axi_adrv9009_ip.tcl - axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl - axi_hdmi_tx/axi_hdmi_tx_ip.tcl - xilinx/axi_adxcvr/Makefile - xilinx/axi_adxcvr/axi_adxcvr_ip.tcl - xilinx/util_adxcvr/Makefile - xilinx/util_adxcvr/util_adxcvr_ip.tcl
2019-03-14 15:25:36 +00:00
adi_ip_bd util_adxcvr "bd/bd.tcl"
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
library: Add link to wiki for IPs
2021-10-20 15:08:35 +00:00
set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_xcvr} [ipx::current_core]
account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores
2022-03-18 21:10:26 +00:00
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
xilinx/util_adxcvr: 204C link support for GTY4 Set channel parameters based on link mode (1 - 204b or 2 - 204c).
2021-04-19 13:57:55 +00:00
set cc [ipx::current_core]
# Arrange GUI page layout
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
# Link layer mode
set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $page0
set_property -dict [list \
"display_name" "Link Layer mode" \
"tooltip" "Link Layer mode" \
"widget" "comboBox" \
] $p
set_property -dict [list \
value_validation_type pairs \
value_validation_pairs {64B66B 2 8B10B 1} \
] [ipx::get_user_parameters $p -of_objects $cc]
# Data width selection
set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc]
set_property -dict [list \
enablement_tcl_expr {$LINK_MODE==1} \
value_tcl_expr {expr $LINK_MODE*4} \
] $param
xilinx:adxcvr: PRBS support The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal PRBS generators and checkers allowing the testing the multi-gigabit serial link at the physical layer without the need of the link layer bringup.
2020-12-18 14:43:28 +00:00
util_adxcvr: Add LANE_RATE parameter so it can be used for automatic constraint generation Add separate LANE_RATE for TX and RX
2021-04-30 08:49:21 +00:00
set p [ipgui::get_guiparamspec -name "RX_LANE_RATE" -component $cc]
ipgui::move_param -component $cc -order 1 $p -parent $page0
set_property -dict [list \
display_name {Rx Lane Rate (Gbps)} \
widget {textEdit} \
] $p
set_property -dict [list \
value_resolve_type user \
value 12.5 \
value_format float \
] [ipx::get_user_parameters $p -of_objects $cc]
set p [ipgui::get_guiparamspec -name "TX_LANE_RATE" -component $cc]
ipgui::move_param -component $cc -order 2 $p -parent $page0
set_property -dict [list \
display_name {Tx Lane Rate (Gbps)} \
widget {textEdit} \
] $p
set_property -dict [list \
value_resolve_type user \
value 12.5 \
value_format float \
] [ipx::get_user_parameters $p -of_objects $cc]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
ipx::remove_all_bus_interface [ipx::current_core]
axi_*: Infer clock and reset signals of an IP A clock sink must be connected to clock source, and a reset sink to reset source, otherwise the tool will throw a synthesis warning. By properly inferring all the reset and clock signals of an IP, we can get rid of unwanted warning messages. The following IPs tcl script was updated: - axi_ad9434 - axi_hdmi_tx - util_cpack - util_adxcvr - axi_ad6676 - axi_ad9625 - axi_ad9379 - axi_ad9265 - util_tdd_sync - util_rfifo - util_wfifo - axi_ad9361 - axi_ad9467 - util_upack - axi_dacfifo - axi_ad9152 - axi_ad9680 - util_clkdiv - axi_ad9122 - axi_ad9684 - axi_mc_speed - axi_mc_current_monitor - axi_mc_controller - util_gmii_to_rgmii - util_adxcvr - axi_ad9379 - axi_hdmi - library - axi_fmcadc5_sync - util_adcfifo - util_mfifo - axi_jesd204_rx - axi_jesd204_tx - axi_ad9361 - axi_adxcvr_ip
2018-02-15 08:41:14 +00:00
ipx::infer_bus_interface up_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
library/jesd204: Updated jesd to support more lanes Modified the maximum number of supported lanes up to 32 lanes for every JESD layer Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-03-01 14:47:44 +00:00
for {set n 0} {$n < 32} {incr n} {
ipx::infer_bus_interface cpll_ref_clk_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
if {($n%4) == 0} {
ipx::infer_bus_interface qpll_ref_clk_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
}
}
for {set n 0} {$n < 32} {incr n} {
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
ipx::infer_bus_interface rx_clk_2x_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_2x_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_div2_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_div2_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
}
axi_*: Infer clock and reset signals of an IP A clock sink must be connected to clock source, and a reset sink to reset source, otherwise the tool will throw a synthesis warning. By properly inferring all the reset and clock signals of an IP, we can get rid of unwanted warning messages. The following IPs tcl script was updated: - axi_ad9434 - axi_hdmi_tx - util_cpack - util_adxcvr - axi_ad6676 - axi_ad9625 - axi_ad9379 - axi_ad9265 - util_tdd_sync - util_rfifo - util_wfifo - axi_ad9361 - axi_ad9467 - util_upack - axi_dacfifo - axi_ad9152 - axi_ad9680 - util_clkdiv - axi_ad9122 - axi_ad9684 - axi_mc_speed - axi_mc_current_monitor - axi_mc_controller - util_gmii_to_rgmii - util_adxcvr - axi_ad9379 - axi_hdmi - library - axi_fmcadc5_sync - util_adcfifo - util_mfifo - axi_jesd204_rx - axi_jesd204_tx - axi_ad9361 - axi_adxcvr_ip
2018-02-15 08:41:14 +00:00
ipx::infer_bus_interface up_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
library/jesd204: Updated jesd to support more lanes Modified the maximum number of supported lanes up to 32 lanes for every JESD layer Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-03-01 14:47:44 +00:00
for {set n 0} {$n < 32} {incr n} {
ipx::infer_bus_interface up_rx_rst_$n xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_$n xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_$n xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
if {($n%4) == 0} {
ipx::infer_bus_interface up_qpll_rst_$n xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
}
}
for {set n 0} {$n < 32} {incr n} {
axi_adxcvr_ip.tcl util_adxcvr_ip.tcl: Fixed asynchronous resets critical warnings in XCVR
2021-09-16 10:56:00 +00:00
if {($n%4) == 0} {
library/jesd204: Updated jesd to support more lanes Modified the maximum number of supported lanes up to 32 lanes for every JESD layer Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-03-01 14:47:44 +00:00
ipx::associate_bus_interfaces -clock cpll_ref_clk_${n} -reset up_qpll_rst_${n} -remove [ipx::current_core]
axi_adxcvr_ip.tcl util_adxcvr_ip.tcl: Fixed asynchronous resets critical warnings in XCVR
2021-09-16 10:56:00 +00:00
}
ipx::associate_bus_interfaces -clock cpll_ref_clk_${n} -reset up_cpll_rst_${n} -remove [ipx::current_core]
}
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
library/jesd204: Updated jesd to support more lanes Modified the maximum number of supported lanes up to 32 lanes for every JESD layer Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-03-01 14:47:44 +00:00
for {set n 0} {$n < 32} {incr n} {
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
if {($n%4) == 0} {
adi_ip.tcl: Use analog.com for interface vendor Currently the scripts use 'analog.com' as the vendor property for IP cores, but 'ADI' for interfaces. Make things consistent by using 'analog.com' for both interfaces as well as IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-22 14:41:58 +00:00
adi_if_infer_bus analog.com:interface:if_xcvr_cm slave up_cm_${n} [list \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
"enb up_cm_enb_${n} "\
"addr up_cm_addr_${n} "\
"wr up_cm_wr_${n} "\
"wdata up_cm_wdata_${n} "\
"rdata up_cm_rdata_${n} "\
"ready up_cm_ready_${n} "]
}
adi_ip.tcl: Use analog.com for interface vendor Currently the scripts use 'analog.com' as the vendor property for IP cores, but 'ADI' for interfaces. Make things consistent by using 'analog.com' for both interfaces as well as IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-22 14:41:58 +00:00
adi_if_infer_bus analog.com:interface:if_xcvr_cm slave up_es_${n} [list \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
"enb up_es_enb_${n} "\
"addr up_es_addr_${n} "\
"wr up_es_wr_${n} "\
"wdata up_es_wdata_${n} "\
"rdata up_es_rdata_${n} "\
axi/util_adxcvr: Add register to control eyescan reset
2018-11-08 13:54:15 +00:00
"reset up_es_reset_${n} "\
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
"ready up_es_ready_${n} "]
adi_ip.tcl: Use analog.com for interface vendor Currently the scripts use 'analog.com' as the vendor property for IP cores, but 'ADI' for interfaces. Make things consistent by using 'analog.com' for both interfaces as well as IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-22 14:41:58 +00:00
adi_if_infer_bus analog.com:interface:if_xcvr_ch slave up_rx_${n} [list \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
"pll_locked up_rx_pll_locked_${n} "\
"rst up_rx_rst_${n} "\
"user_ready up_rx_user_ready_${n} "\
"rst_done up_rx_rst_done_${n} "\
xilinx:adxcvr: PRBS support The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal PRBS generators and checkers allowing the testing the multi-gigabit serial link at the physical layer without the need of the link layer bringup.
2020-12-18 14:43:28 +00:00
"prbssel up_rx_prbssel_${n} "\
"prbscntreset up_rx_prbscntreset_${n}"\
"prbserr up_rx_prbserr_${n} "\
"prbslocked up_rx_prbslocked_${n} "\
adxcvr: Increase version to 17.5.a Add suport for XCVR phase adjust buffer status: - Expose TXBUFSTATUS and RXBUFSTATUS - Create RXBUFSTATUS_RST flag for clearing RXBUFSTATUS
2021-10-01 14:41:30 +00:00
"bufstatus up_rx_bufstatus_${n} "\
"bufstatus_rst up_rx_bufstatus_rst_${n}"\
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
"lpm_dfe_n up_rx_lpm_dfe_n_${n} "\
"rate up_rx_rate_${n} "\
"sys_clk_sel up_rx_sys_clk_sel_${n} "\
"out_clk_sel up_rx_out_clk_sel_${n} "\
"enb up_rx_enb_${n} "\
"addr up_rx_addr_${n} "\
"wr up_rx_wr_${n} "\
"wdata up_rx_wdata_${n} "\
"rdata up_rx_rdata_${n} "\
"ready up_rx_ready_${n} "]
adi_ip.tcl: Use analog.com for interface vendor Currently the scripts use 'analog.com' as the vendor property for IP cores, but 'ADI' for interfaces. Make things consistent by using 'analog.com' for both interfaces as well as IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-22 14:41:58 +00:00
adi_if_infer_bus analog.com:interface:if_xcvr_ch slave up_tx_${n} [list \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
"pll_locked up_tx_pll_locked_${n} "\
"rst up_tx_rst_${n} "\
"user_ready up_tx_user_ready_${n} "\
"rst_done up_tx_rst_done_${n} "\
xilinx:adxcvr: PRBS support The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal PRBS generators and checkers allowing the testing the multi-gigabit serial link at the physical layer without the need of the link layer bringup.
2020-12-18 14:43:28 +00:00
"prbsforceerr up_tx_prbsforceerr_${n}"\
"prbssel up_tx_prbssel_${n} "\
adxcvr: Increase version to 17.5.a Add suport for XCVR phase adjust buffer status: - Expose TXBUFSTATUS and RXBUFSTATUS - Create RXBUFSTATUS_RST flag for clearing RXBUFSTATUS
2021-10-01 14:41:30 +00:00
"bufstatus up_tx_bufstatus_${n} "\
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
"lpm_dfe_n up_tx_lpm_dfe_n_${n} "\
"rate up_tx_rate_${n} "\
"sys_clk_sel up_tx_sys_clk_sel_${n} "\
"out_clk_sel up_tx_out_clk_sel_${n} "\
axi|util_adxcvr: Expose TX configurable driver ports Expose the TX configurable driver ports, more specifically the TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This provides a soft tunning capability of the transmit side of the transceivers, in cases where the insertion loss of the channel is too high or low, comparing to the default value supported by the default configuration of the GTs. You can find information about these configuration ports under the section called 'TX Configurable Driver' in the GT transceivers user guide. (UG476, UG576)
2018-10-01 15:36:39 +00:00
"tx_diffctrl up_tx_diffctrl_${n} "\
"tx_postcursor up_tx_postcursor_${n} "\
"tx_precursor up_tx_precursor_${n} "\
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
"enb up_tx_enb_${n} "\
"addr up_tx_addr_${n} "\
"wr up_tx_wr_${n} "\
"wdata up_tx_wdata_${n} "\
"rdata up_tx_rdata_${n} "\
"ready up_tx_ready_${n} "]
ipx::add_bus_interface rx_${n} [ipx::current_core]
set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 \
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus:1.0 \
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
set_property interface_mode master [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
ipx::add_port_map rxcharisk [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
set_property physical_name rx_charisk_${n} [ipx::get_port_maps rxcharisk -of_objects \
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
ipx::add_port_map rxnotintable [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
set_property physical_name rx_notintable_${n} [ipx::get_port_maps rxnotintable -of_objects \
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
ipx::add_port_map rxdisperr [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
set_property physical_name rx_disperr_${n} [ipx::get_port_maps rxdisperr -of_objects \
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
ipx::add_port_map rxdata [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
set_property physical_name rx_data_${n} [ipx::get_port_maps rxdata -of_objects \
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
xilinx/util_adxcvr: 204C link support for GTY4 Set channel parameters based on link mode (1 - 204b or 2 - 204c).
2021-04-19 13:57:55 +00:00
ipx::add_port_map rxheader [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
set_property physical_name rx_header_${n} [ipx::get_port_maps rxheader -of_objects \
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
ipx::add_port_map rxblock_sync [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
set_property physical_name rx_block_sync_${n} [ipx::get_port_maps rxblock_sync -of_objects \
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
ipx::add_bus_interface tx_${n} [ipx::current_core]
set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 \
[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus:1.0 \
[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
set_property interface_mode slave [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
ipx::add_port_map txcharisk [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
set_property physical_name tx_charisk_${n} [ipx::get_port_maps txcharisk -of_objects \
[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]]
ipx::add_port_map txdata [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
set_property physical_name tx_data_${n} [ipx::get_port_maps txdata -of_objects \
[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]]
xilinx/util_adxcvr: 204C link support for GTY4 Set channel parameters based on link mode (1 - 204b or 2 - 204c).
2021-04-19 13:57:55 +00:00
ipx::add_port_map txheader [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
set_property physical_name tx_header_${n} [ipx::get_port_maps txheader -of_objects \
[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
}
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
[ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
[ipx::get_bus_interfaces up_rx_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
[ipx::get_bus_interfaces rx_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports rx_0_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_0 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_0 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_0 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
[ipx::get_ports up_rx_rst_0 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
[ipx::get_bus_interfaces up_tx_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
[ipx::get_bus_interfaces tx_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports tx_0* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_0 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_0 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
[ipx::get_ports up_tx_rst_0 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports cpll_ref_clk_0 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_cpll_rst_0 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_0 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_0 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_0 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_0 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports qpll_ref_clk_0 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_qpll_rst_0 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
[ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
[ipx::get_bus_interfaces up_rx_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
[ipx::get_bus_interfaces rx_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports rx_1_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_1 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_1 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_1 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
[ipx::get_ports up_rx_rst_1 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
[ipx::get_bus_interfaces up_tx_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
[ipx::get_bus_interfaces tx_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports tx_1* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_1 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_1 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
[ipx::get_ports up_tx_rst_1 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports cpll_ref_clk_1 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_cpll_rst_1 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_1 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_1 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_1 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_1 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
[ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
[ipx::get_bus_interfaces up_rx_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
[ipx::get_bus_interfaces rx_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports rx_2_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_2 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_2 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_2 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
[ipx::get_ports up_rx_rst_2 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
[ipx::get_bus_interfaces up_tx_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
[ipx::get_bus_interfaces tx_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports tx_2* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_2 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_2 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
[ipx::get_ports up_tx_rst_2 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports cpll_ref_clk_2 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_cpll_rst_2 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_2 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_2 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_2 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_2 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
[ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
[ipx::get_bus_interfaces up_rx_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
[ipx::get_bus_interfaces rx_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports rx_3_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_3 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_3 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_3 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
[ipx::get_ports up_rx_rst_3 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
[ipx::get_bus_interfaces up_tx_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
[ipx::get_bus_interfaces tx_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports tx_3* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_3 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_3 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
[ipx::get_ports up_tx_rst_3 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports cpll_ref_clk_3 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_cpll_rst_3 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_3 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_3 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_3 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_3 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
[ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
[ipx::get_bus_interfaces up_rx_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
[ipx::get_bus_interfaces rx_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports rx_4_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_4 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_4 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_4 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
[ipx::get_ports up_rx_rst_4 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
[ipx::get_bus_interfaces up_tx_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
[ipx::get_bus_interfaces tx_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports tx_4* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_4 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_4 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
[ipx::get_ports up_tx_rst_4 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports cpll_ref_clk_4 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_cpll_rst_4 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_4 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_4 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_4 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_4 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports qpll_ref_clk_4 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_qpll_rst_4 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
[ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
[ipx::get_bus_interfaces up_rx_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
[ipx::get_bus_interfaces rx_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports rx_5_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_5 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_5 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_5 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
[ipx::get_ports up_rx_rst_5 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
[ipx::get_bus_interfaces up_tx_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
[ipx::get_bus_interfaces tx_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports tx_5* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_5 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_5 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
[ipx::get_ports up_tx_rst_5 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports cpll_ref_clk_5 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_cpll_rst_5 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_5 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_5 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_5 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_5 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
[ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
[ipx::get_bus_interfaces up_rx_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
[ipx::get_bus_interfaces rx_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports rx_6_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_6 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_6 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_6 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
[ipx::get_ports up_rx_rst_6 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
[ipx::get_bus_interfaces up_tx_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
[ipx::get_bus_interfaces tx_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports tx_6* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_6 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_6 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
[ipx::get_ports up_tx_rst_6 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports cpll_ref_clk_6 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_cpll_rst_6 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_6 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_6 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_6 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_6 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
[ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
[ipx::get_bus_interfaces up_rx_7 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
[ipx::get_bus_interfaces rx_7 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports rx_7_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_7 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_7 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_7 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
[ipx::get_ports up_rx_rst_7 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
[ipx::get_bus_interfaces up_tx_7 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
[ipx::get_bus_interfaces tx_7 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports tx_7* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_7 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_7 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
[ipx::get_ports up_tx_rst_7 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports cpll_ref_clk_7 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_cpll_rst_7 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_7 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_7 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_7 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_7 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
[ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
[ipx::get_bus_interfaces up_rx_8 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
[ipx::get_bus_interfaces rx_8 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports rx_8_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_8 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_8 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_8 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
[ipx::get_ports up_rx_rst_8 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
[ipx::get_bus_interfaces up_tx_8 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
[ipx::get_bus_interfaces tx_8 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports tx_8* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_8 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_8 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
[ipx::get_ports up_tx_rst_8 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports cpll_ref_clk_8 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_cpll_rst_8 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_8 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_8 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_8 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_8 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports qpll_ref_clk_8 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_qpll_rst_8 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
[ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
[ipx::get_bus_interfaces up_rx_9 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
[ipx::get_bus_interfaces rx_9 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports rx_9_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_9 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_9 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_9 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
[ipx::get_ports up_rx_rst_9 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
[ipx::get_bus_interfaces up_tx_9 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
[ipx::get_bus_interfaces tx_9 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports tx_9* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_9 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_9 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
[ipx::get_ports up_tx_rst_9 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports cpll_ref_clk_9 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_cpll_rst_9 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_9 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_9 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_9 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_9 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
[ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
[ipx::get_bus_interfaces up_rx_10 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
[ipx::get_bus_interfaces rx_10 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports rx_10_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_10 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_10 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_10 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
[ipx::get_ports up_rx_rst_10 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
[ipx::get_bus_interfaces up_tx_10 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
[ipx::get_bus_interfaces tx_10 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports tx_10* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_10 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_10 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
[ipx::get_ports up_tx_rst_10 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports cpll_ref_clk_10 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_cpll_rst_10 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_10 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_10 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_10 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_10 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
[ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
[ipx::get_bus_interfaces up_rx_11 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
[ipx::get_bus_interfaces rx_11 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports rx_11_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_11 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_11 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_11 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
[ipx::get_ports up_rx_rst_11 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
[ipx::get_bus_interfaces up_tx_11 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
[ipx::get_bus_interfaces tx_11 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports tx_11* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_11 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_11 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
[ipx::get_ports up_tx_rst_11 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports cpll_ref_clk_11 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_cpll_rst_11 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_11 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_11 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_11 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_11 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
[ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
[ipx::get_bus_interfaces up_rx_12 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
[ipx::get_bus_interfaces rx_12 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports rx_12_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_12 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_12 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_12 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
[ipx::get_ports up_rx_rst_12 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
[ipx::get_bus_interfaces up_tx_12 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
[ipx::get_bus_interfaces tx_12 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports tx_12* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_12 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_12 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
[ipx::get_ports up_tx_rst_12 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports cpll_ref_clk_12 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_cpll_rst_12 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_12 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_12 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_12 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_12 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports qpll_ref_clk_12 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_qpll_rst_12 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
[ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
[ipx::get_bus_interfaces up_rx_13 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
[ipx::get_bus_interfaces rx_13 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports rx_13_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_13 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_13 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_13 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
[ipx::get_ports up_rx_rst_13 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
[ipx::get_bus_interfaces up_tx_13 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
[ipx::get_bus_interfaces tx_13 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports tx_13* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_13 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_13 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
[ipx::get_ports up_tx_rst_13 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports cpll_ref_clk_13 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_cpll_rst_13 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_13 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_13 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_13 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_13 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
[ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
[ipx::get_bus_interfaces up_rx_14 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
[ipx::get_bus_interfaces rx_14 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports rx_14_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_14 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_14 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_14 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
[ipx::get_ports up_rx_rst_14 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
[ipx::get_bus_interfaces up_tx_14 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
[ipx::get_bus_interfaces tx_14 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports tx_14* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_14 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_14 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
[ipx::get_ports up_tx_rst_14 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports cpll_ref_clk_14 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_cpll_rst_14 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_14 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_14 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_14 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_14 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
[ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
[ipx::get_bus_interfaces up_rx_15 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
[ipx::get_bus_interfaces rx_15 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports rx_15_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_15 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_15 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_15 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
[ipx::get_ports up_rx_rst_15 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
[ipx::get_bus_interfaces up_tx_15 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
[ipx::get_bus_interfaces tx_15 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
[ipx::get_ports tx_15* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_15 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_15 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Don't show reset ports for disabled lanes
2018-03-06 13:46:49 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
[ipx::get_ports up_tx_rst_15 -of_objects [ipx::current_core]] \
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
set_property enablement_dependency \
xilinx/util_adxcvr: Update enablement dependencies
2016-11-22 15:33:40 +00:00
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15) or \
util_adxcvr: regenerate from script
2016-11-22 16:21:04 +00:00
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15)} \
xcvr updates- board procedure
2016-11-22 19:43:36 +00:00
[ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]] \
library: Delete all adi_ip_constraint process call
2017-04-06 09:36:47 +00:00
[ipx::get_ports up_cpll_rst_15 -of_objects [ipx::current_core]]
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
util_adxcvr: Add 204C support for GTH3/4 For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parameters
2021-05-17 10:27:33 +00:00
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_15 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_15 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_15 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_15 -of_objects [ipx::current_core]] \
library/jesd204: Updated jesd to support more lanes Modified the maximum number of supported lanes up to 32 lanes for every JESD layer Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-03-01 14:47:44 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16} \
[ipx::get_bus_interfaces up_es_16 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16} \
[ipx::get_bus_interfaces up_rx_16 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16} \
[ipx::get_bus_interfaces rx_16 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16} \
[ipx::get_ports rx_16_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_16 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_16 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_16 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16} \
[ipx::get_ports up_rx_rst_16 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16} \
[ipx::get_bus_interfaces up_tx_16 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16} \
[ipx::get_bus_interfaces tx_16 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16} \
[ipx::get_ports tx_16* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_16 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_16 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16} \
[ipx::get_ports up_tx_rst_16 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16)} \
[ipx::get_ports cpll_ref_clk_16 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_16 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_16 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_16 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_16 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_16 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16)} \
[ipx::get_ports qpll_ref_clk_16 -of_objects [ipx::current_core]] \
[ipx::get_ports up_qpll_rst_16 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16)} \
[ipx::get_bus_interfaces up_cm_16 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17} \
[ipx::get_bus_interfaces up_es_17 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17} \
[ipx::get_bus_interfaces up_rx_17 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17} \
[ipx::get_bus_interfaces rx_17 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17} \
[ipx::get_ports rx_17_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_17 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_17 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_17 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17} \
[ipx::get_ports up_rx_rst_17 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 17} \
[ipx::get_bus_interfaces up_tx_17 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 17} \
[ipx::get_bus_interfaces tx_17 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 17} \
[ipx::get_ports tx_17* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_17 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_17 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 17} \
[ipx::get_ports up_tx_rst_17 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 17) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17)} \
[ipx::get_ports cpll_ref_clk_17 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_17 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_17 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_17 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 17) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_17 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_17 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18} \
[ipx::get_bus_interfaces up_es_18 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18} \
[ipx::get_bus_interfaces up_rx_18 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18} \
[ipx::get_bus_interfaces rx_18 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18} \
[ipx::get_ports rx_18_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_18 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_18 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_18 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18} \
[ipx::get_ports up_rx_rst_18 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 18} \
[ipx::get_bus_interfaces up_tx_18 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 18} \
[ipx::get_bus_interfaces tx_18 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 18} \
[ipx::get_ports tx_18* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_18 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_18 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 18} \
[ipx::get_ports up_tx_rst_18 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 18) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18)} \
[ipx::get_ports cpll_ref_clk_18 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_18 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_18 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_18 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 18) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_18 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_18 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19} \
[ipx::get_bus_interfaces up_es_19 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19} \
[ipx::get_bus_interfaces up_rx_19 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19} \
[ipx::get_bus_interfaces rx_19 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19} \
[ipx::get_ports rx_19_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_19 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_19 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_19 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19} \
[ipx::get_ports up_rx_rst_19 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 19} \
[ipx::get_bus_interfaces up_tx_19 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 19} \
[ipx::get_bus_interfaces tx_19 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 19} \
[ipx::get_ports tx_19* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_19 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_19 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 19} \
[ipx::get_ports up_tx_rst_19 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 19) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19)} \
[ipx::get_ports cpll_ref_clk_19 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_19 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_19 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_19 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 19) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_19 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_19 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20} \
[ipx::get_bus_interfaces up_es_20 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20} \
[ipx::get_bus_interfaces up_rx_20 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20} \
[ipx::get_bus_interfaces rx_20 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20} \
[ipx::get_ports rx_20_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_20 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_20 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_20 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20} \
[ipx::get_ports up_rx_rst_20 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20} \
[ipx::get_bus_interfaces up_tx_20 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20} \
[ipx::get_bus_interfaces tx_20 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20} \
[ipx::get_ports tx_20* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_20 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_20 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20} \
[ipx::get_ports up_tx_rst_20 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20)} \
[ipx::get_ports cpll_ref_clk_20 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_20 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_20 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_20 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_20 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_20 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20)} \
[ipx::get_ports qpll_ref_clk_20 -of_objects [ipx::current_core]] \
[ipx::get_ports up_qpll_rst_20 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20)} \
[ipx::get_bus_interfaces up_cm_20 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21} \
[ipx::get_bus_interfaces up_es_21 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21} \
[ipx::get_bus_interfaces up_rx_21 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21} \
[ipx::get_bus_interfaces rx_21 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21} \
[ipx::get_ports rx_21_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_21 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_21 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_21 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21} \
[ipx::get_ports up_rx_rst_21 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 21} \
[ipx::get_bus_interfaces up_tx_21 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 21} \
[ipx::get_bus_interfaces tx_21 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 21} \
[ipx::get_ports tx_21* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_21 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_21 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 21} \
[ipx::get_ports up_tx_rst_21 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 21) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21)} \
[ipx::get_ports cpll_ref_clk_21 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_21 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_21 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_21 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 21) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_21 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_21 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22} \
[ipx::get_bus_interfaces up_es_22 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22} \
[ipx::get_bus_interfaces up_rx_22 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22} \
[ipx::get_bus_interfaces rx_22 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22} \
[ipx::get_ports rx_22_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_22 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_22 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_22 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22} \
[ipx::get_ports up_rx_rst_22 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 22} \
[ipx::get_bus_interfaces up_tx_22 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 22} \
[ipx::get_bus_interfaces tx_22 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 22} \
[ipx::get_ports tx_22* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_22 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_22 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 22} \
[ipx::get_ports up_tx_rst_22 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 22) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22)} \
[ipx::get_ports cpll_ref_clk_22 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_22 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_22 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_22 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 22) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_22 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_22 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23} \
[ipx::get_bus_interfaces up_es_23 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23} \
[ipx::get_bus_interfaces up_rx_23 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23} \
[ipx::get_bus_interfaces rx_23 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23} \
[ipx::get_ports rx_23_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_23 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_23 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_23 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23} \
[ipx::get_ports up_rx_rst_23 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 23} \
[ipx::get_bus_interfaces up_tx_23 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 23} \
[ipx::get_bus_interfaces tx_23 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 23} \
[ipx::get_ports tx_23* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_23 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_23 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 23} \
[ipx::get_ports up_tx_rst_23 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 23) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23)} \
[ipx::get_ports cpll_ref_clk_23 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_23 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_23 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_23 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 23) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_23 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_23 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24} \
[ipx::get_bus_interfaces up_es_24 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24} \
[ipx::get_bus_interfaces up_rx_24 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24} \
[ipx::get_bus_interfaces rx_24 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24} \
[ipx::get_ports rx_24_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_24 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_24 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_24 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24} \
[ipx::get_ports up_rx_rst_24 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24} \
[ipx::get_bus_interfaces up_tx_24 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24} \
[ipx::get_bus_interfaces tx_24 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24} \
[ipx::get_ports tx_24* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_24 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_24 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24} \
[ipx::get_ports up_tx_rst_24 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24)} \
[ipx::get_ports cpll_ref_clk_24 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_24 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_24 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_24 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_24 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_24 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24)} \
[ipx::get_ports qpll_ref_clk_24 -of_objects [ipx::current_core]] \
[ipx::get_ports up_qpll_rst_24 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24)} \
[ipx::get_bus_interfaces up_cm_24 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25} \
[ipx::get_bus_interfaces up_es_25 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25} \
[ipx::get_bus_interfaces up_rx_25 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25} \
[ipx::get_bus_interfaces rx_25 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25} \
[ipx::get_ports rx_25_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_25 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_25 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_25 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25} \
[ipx::get_ports up_rx_rst_25 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 25} \
[ipx::get_bus_interfaces up_tx_25 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 25} \
[ipx::get_bus_interfaces tx_25 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 25} \
[ipx::get_ports tx_25* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_25 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_25 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 25} \
[ipx::get_ports up_tx_rst_25 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 25) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25)} \
[ipx::get_ports cpll_ref_clk_25 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_25 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_25 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_25 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 25) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_25 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_25 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26} \
[ipx::get_bus_interfaces up_es_26 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26} \
[ipx::get_bus_interfaces up_rx_26 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26} \
[ipx::get_bus_interfaces rx_26 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26} \
[ipx::get_ports rx_26_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_26 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_26 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_26 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26} \
[ipx::get_ports up_rx_rst_26 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 26} \
[ipx::get_bus_interfaces up_tx_26 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 26} \
[ipx::get_bus_interfaces tx_26 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 26} \
[ipx::get_ports tx_26* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_26 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_26 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 26} \
[ipx::get_ports up_tx_rst_26 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 26) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26)} \
[ipx::get_ports cpll_ref_clk_26 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_26 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_26 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_26 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 26) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_26 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_26 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27} \
[ipx::get_bus_interfaces up_es_27 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27} \
[ipx::get_bus_interfaces up_rx_27 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27} \
[ipx::get_bus_interfaces rx_27 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27} \
[ipx::get_ports rx_27_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_27 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_27 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_27 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27} \
[ipx::get_ports up_rx_rst_27 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 27} \
[ipx::get_bus_interfaces up_tx_27 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 27} \
[ipx::get_bus_interfaces tx_27 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 27} \
[ipx::get_ports tx_27* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_27 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_27 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 27} \
[ipx::get_ports up_tx_rst_27 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 27) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27)} \
[ipx::get_ports cpll_ref_clk_27 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_27 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_27 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_27 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 27) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_27 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_27 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28} \
[ipx::get_bus_interfaces up_es_28 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28} \
[ipx::get_bus_interfaces up_rx_28 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28} \
[ipx::get_bus_interfaces rx_28 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28} \
[ipx::get_ports rx_28_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_28 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_28 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_28 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28} \
[ipx::get_ports up_rx_rst_28 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28} \
[ipx::get_bus_interfaces up_tx_28 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28} \
[ipx::get_bus_interfaces tx_28 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28} \
[ipx::get_ports tx_28* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_28 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_28 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28} \
[ipx::get_ports up_tx_rst_28 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28)} \
[ipx::get_ports cpll_ref_clk_28 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_28 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_28 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_28 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_28 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_28 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28)} \
[ipx::get_ports qpll_ref_clk_28 -of_objects [ipx::current_core]] \
[ipx::get_ports up_qpll_rst_28 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28)} \
[ipx::get_bus_interfaces up_cm_28 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29} \
[ipx::get_bus_interfaces up_es_29 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29} \
[ipx::get_bus_interfaces up_rx_29 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29} \
[ipx::get_bus_interfaces rx_29 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29} \
[ipx::get_ports rx_29_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_29 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_29 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_29 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29} \
[ipx::get_ports up_rx_rst_29 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 29} \
[ipx::get_bus_interfaces up_tx_29 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 29} \
[ipx::get_bus_interfaces tx_29 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 29} \
[ipx::get_ports tx_29* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_29 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_29 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 29} \
[ipx::get_ports up_tx_rst_29 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 29) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29)} \
[ipx::get_ports cpll_ref_clk_29 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_29 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_29 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_29 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 29) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_29 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_29 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30} \
[ipx::get_bus_interfaces up_es_30 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30} \
[ipx::get_bus_interfaces up_rx_30 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30} \
[ipx::get_bus_interfaces rx_30 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30} \
[ipx::get_ports rx_30_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_30 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_30 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_30 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30} \
[ipx::get_ports up_rx_rst_30 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 30} \
[ipx::get_bus_interfaces up_tx_30 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 30} \
[ipx::get_bus_interfaces tx_30 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 30} \
[ipx::get_ports tx_30* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_30 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_30 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 30} \
[ipx::get_ports up_tx_rst_30 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 30) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30)} \
[ipx::get_ports cpll_ref_clk_30 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_30 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_30 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_30 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 30) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_30 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_30 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31} \
[ipx::get_bus_interfaces up_es_31 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31} \
[ipx::get_bus_interfaces up_rx_31 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31} \
[ipx::get_bus_interfaces rx_31 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31} \
[ipx::get_ports rx_31_* -of_objects [ipx::current_core]] \
[ipx::get_ports rx_clk_31 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_calign_31 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_31 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31} \
[ipx::get_ports up_rx_rst_31 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 31} \
[ipx::get_bus_interfaces up_tx_31 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 31} \
[ipx::get_bus_interfaces tx_31 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 31} \
[ipx::get_ports tx_31* -of_objects [ipx::current_core]] \
[ipx::get_ports tx_clk_31 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_31 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 31} \
[ipx::get_ports up_tx_rst_31 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 31) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31)} \
[ipx::get_ports cpll_ref_clk_31 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_31 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports rx_clk_2x_31 -of_objects [ipx::current_core]] \
[ipx::get_ports rx_out_clk_div2_31 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 31) and \
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
[ipx::get_ports tx_clk_2x_31 -of_objects [ipx::current_core]] \
[ipx::get_ports tx_out_clk_div2_31 -of_objects [ipx::current_core]] \
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
adi_add_auto_fpga_spec_params
library/xilinx/util_adxcvr: merge GTY and GTH prefixed parameter parameters with same names were duplicated with transceiver specific names due different default values. This does not scales very well. Use same name for the parameters as for other parameters and do the default value handling in the IP configuration layer.
2019-11-14 13:22:09 +00:00
set cc [ipx::current_core]
set param [ipx::get_user_parameters CH_HSPMUX -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2424 : \
{$XCVR_TYPE == 9} ? 0x2020 : 0x0]]} \
] $param
set param [ipx::get_user_parameters PPF0_CFG -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x800 : 0x600]]} \
] $param
set param [ipx::get_user_parameters RXPI_CFG0 -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2 : \
{$XCVR_TYPE == 9} ? 0x100 : 0x0]]} \
] $param
set param [ipx::get_user_parameters RXPI_CFG1 -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x15 : 0x0]]} \
] $param
set param [ipx::get_user_parameters RTX_BUF_CML_CTRL -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x3 : 0x0]]} \
] $param
util_adxcvr: add GTY4 parameters for 15.5Gbps lanerate
2019-11-15 13:17:23 +00:00
set param [ipx::get_user_parameters QPLL_LPF -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x37f : 0x137]]} \
] $param
set param [ipx::get_user_parameters RXCDR_CFG3_GEN2 -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x1a ]]} \
] $param
set param [ipx::get_user_parameters RXCDR_CFG3_GEN4 -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x24 ]]} \
] $param
set param [ipx::get_user_parameters TX_PI_BIASSET -of_objects $cc]
set_property -dict [list \
value_tcl_expr {expr {$XCVR_TYPE == 9} ? 0 : 1} \
] $param
Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync
2019-01-11 08:54:16 +00:00
ipx::create_xgui_files [ipx::current_core]
util_adxcvr- system verilog interfaces
2016-06-16 20:41:43 +00:00
ipx::save_core [ipx::current_core]