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pluto_hdl_adi/library/axi_gpreg/axi_gpreg_constr.xdc

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axi_gpreg: added constraints
2015-11-05 16:27:46 +00:00
constraints: Update constraints Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.
2017-02-24 11:43:32 +00:00
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *ad_rst_sync*}]
axi_gpreg: added constraints
2015-11-05 16:27:46 +00:00
set_false_path -from [get_cells -hier -filter {name =~ *up_d_preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]
axi_gpreg- added
2015-11-03 19:07:55 +00:00