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pluto_hdl_adi/projects/ad469x_fmc/zed/system_bd.tcl

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ad469x: Add reference design for ad469x eval board
2020-10-08 13:10:28 +00:00
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
sysid: Upgrade framework, header/ip are now at 2/1.1.a Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl add git branch to internal use area; update log prints; update xilixn projects; fix cn0506 sysid script;
2020-10-09 14:28:10 +00:00
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
ad469x: Add reference design for ad469x eval board
2020-10-08 13:10:28 +00:00
# specify the spi reference clock frequency in MHz
set spi_clk_ref_frequency 160
# specify ADC resolution -- supported resolutions 16 bits
set adc_resolution 16
# specify ADC sampling rate in samples/seconds
set adc_sampling_rate 1000000
adi_project_files ad469x_fmc_zed [list \
"../../../library/common/ad_edge_detect.v" \
"../../../library/util_cdc/sync_bits.v" \
]
sysid: Upgrade framework, header/ip are now at 2/1.1.a Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl add git branch to internal use area; update log prints; update xilixn projects; fix cn0506 sysid script;
2020-10-09 14:28:10 +00:00
ad469x: Add reference design for ad469x eval board
2020-10-08 13:10:28 +00:00
source ../common/ad469x_bd.tcl
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
ad469x: Remove sysid custom string init
2020-10-26 15:15:40 +00:00
sysid_gen_sys_init_file