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pluto_hdl_adi/projects/adrv9371x/zcu102/system_bd.tcl

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adrv9371x_zcu102: Initial commit
2017-08-22 12:48:03 +00:00
adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb
2018-08-10 07:34:45 +00:00
## FIFO depth is 16Mb - 1M samples
set dac_fifo_address_width 17
adrv9371x_zcu102: Initial commit
2017-08-22 12:48:03 +00:00
adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb
2018-08-10 07:34:45 +00:00
## NOTE: With this configuration the #36Kb BRAM utilization is at ~51%
adrv9371x_zcu102: Initial commit
2017-08-22 12:48:03 +00:00
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
sysid: Upgrade framework, header/ip are now at 2/1.1.a Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl add git branch to internal use area; update log prints; update xilixn projects; fix cn0506 sysid script;
2020-10-09 14:28:10 +00:00
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
adrv9371x_zcu102: Initial commit
2017-08-22 12:48:03 +00:00
system_id: deployed ip
2019-06-28 08:41:21 +00:00
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid: Remove cstring init string
2020-09-28 21:10:35 +00:00
sysid_gen_sys_init_file
system_id: deployed ip
2019-06-28 08:41:21 +00:00
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 200
adrv9371x_zcu102: Initial commit
2017-08-22 12:48:03 +00:00
source ../common/adrv9371x_bd.tcl
adrv9371/zcu102: Tune the differential swing of the TX lines
2018-10-03 15:43:30 +00:00
ad_ip_parameter axi_ad9371_tx_xcvr CONFIG.TX_DIFFCTRL 6
adrv9371x: Set correct transceiver type for UltraScale projects Make sure that the axi_adxcvr instances are configured with the same transceiver type as the util_adxcvr. This is necessary for software to be able to detect the transceiver type and support dynamic reconfiguration. It is also necessary for correct eye scan support in the axi_adxcvr block. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-11-10 16:11:46 +00:00
adrv9371x: zcu102: Fix QPLL feedback divider The external reference clock runs at 122.88 MHz by default. This means that the QPLL feedback divider needs to be set to 80 so that the VCO is inside the locking range (9.8 GHz - 16.375 GHz). Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-11-10 16:03:29 +00:00
ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_FBDIV 80
adrv9371x_zcu102: Initial commit
2017-08-22 12:48:03 +00:00
ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_REFCLK_DIV 1