2014-05-19 17:49:49 +00:00
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# fmcomms5
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# master
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2015-03-25 15:42:11 +00:00
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create_bd_port -dir I rx_clk_in_0_p
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create_bd_port -dir I rx_clk_in_0_n
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create_bd_port -dir I rx_frame_in_0_p
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create_bd_port -dir I rx_frame_in_0_n
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create_bd_port -dir I -from 5 -to 0 rx_data_in_0_p
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create_bd_port -dir I -from 5 -to 0 rx_data_in_0_n
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create_bd_port -dir O tx_clk_out_0_p
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create_bd_port -dir O tx_clk_out_0_n
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create_bd_port -dir O tx_frame_out_0_p
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create_bd_port -dir O tx_frame_out_0_n
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create_bd_port -dir O -from 5 -to 0 tx_data_out_0_p
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create_bd_port -dir O -from 5 -to 0 tx_data_out_0_n
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2014-05-19 17:49:49 +00:00
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# slave
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2015-03-25 15:42:11 +00:00
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create_bd_port -dir I rx_clk_in_1_p
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create_bd_port -dir I rx_clk_in_1_n
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create_bd_port -dir I rx_frame_in_1_p
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create_bd_port -dir I rx_frame_in_1_n
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create_bd_port -dir I -from 5 -to 0 rx_data_in_1_p
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create_bd_port -dir I -from 5 -to 0 rx_data_in_1_n
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create_bd_port -dir O tx_clk_out_1_p
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create_bd_port -dir O tx_clk_out_1_n
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create_bd_port -dir O tx_frame_out_1_p
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create_bd_port -dir O tx_frame_out_1_n
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create_bd_port -dir O -from 5 -to 0 tx_data_out_1_p
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create_bd_port -dir O -from 5 -to 0 tx_data_out_1_n
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create_bd_port -dir O sys_100m_resetn
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2014-11-07 11:45:15 +00:00
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2014-05-19 17:49:49 +00:00
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# instances
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set axi_ad9361_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361_0]
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set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9361_0
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set_property -dict [list CONFIG.PCORE_IODELAY_GROUP {dev_0_if_delay_group}] $axi_ad9361_0
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set axi_ad9361_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361_1]
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set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9361_1
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set_property -dict [list CONFIG.PCORE_IODELAY_GROUP {dev_1_if_delay_group}] $axi_ad9361_1
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set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma
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2014-11-07 11:45:15 +00:00
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
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2014-05-19 17:49:49 +00:00
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set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_dac_dma
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set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_adc_dma
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2014-11-07 11:45:15 +00:00
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_adc_dma
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2014-05-19 17:49:49 +00:00
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2014-07-07 18:03:01 +00:00
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set util_adc_pack_0 [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack_0]
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set util_dac_unpack_0 [create_bd_cell -type ip -vlnv analog.com:user:util_dac_unpack:1.0 util_dac_unpack_0]
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2015-03-25 15:42:11 +00:00
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# constants for avoiding errors when validating bd
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2015-03-31 14:42:44 +00:00
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2015-03-25 15:42:11 +00:00
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set constant_1bit [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_1bit]
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set_property -dict [list CONFIG.CONST_VAL {0}] $constant_1bit
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2014-05-19 17:49:49 +00:00
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2015-03-25 15:42:11 +00:00
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set constant_32bit [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_32bit]
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set_property -dict [list CONFIG.CONST_WIDTH {32}] $constant_32bit
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set_property -dict [list CONFIG.CONST_VAL {0}] $constant_32bit
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2014-05-19 17:49:49 +00:00
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# connections (ad9361)
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2015-03-25 15:42:11 +00:00
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ad_connect sys_200m_clk axi_ad9361_0/delay_clk
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ad_connect sys_200m_clk axi_ad9361_1/delay_clk
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ad_connect axi_ad9361_0_clk axi_ad9361_0/l_clk
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ad_connect axi_ad9361_1_clk axi_ad9361_1/l_clk
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ad_connect axi_ad9361_0_clk axi_ad9361_0/clk
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ad_connect axi_ad9361_0_clk axi_ad9361_1/clk
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ad_connect axi_ad9361_0_clk util_adc_pack_0/clk
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ad_connect axi_ad9361_0_clk util_dac_unpack_0/clk
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ad_connect axi_ad9361_0_clk axi_ad9361_adc_dma/fifo_wr_clk
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ad_connect axi_ad9361_0_clk axi_ad9361_dac_dma/fifo_rd_clk
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ad_connect sys_cpu_resetn sys_100m_resetn
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ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
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ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
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ad_connect axi_ad9361_0_dac_sync axi_ad9361_0/dac_sync_out
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ad_connect axi_ad9361_0_dac_sync axi_ad9361_0/dac_sync_in
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ad_connect axi_ad9361_0_dac_sync axi_ad9361_1/dac_sync_in
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ad_connect rx_clk_in_0_p axi_ad9361_0/rx_clk_in_p
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ad_connect rx_clk_in_0_n axi_ad9361_0/rx_clk_in_n
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ad_connect rx_frame_in_0_p axi_ad9361_0/rx_frame_in_p
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ad_connect rx_frame_in_0_n axi_ad9361_0/rx_frame_in_n
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ad_connect rx_data_in_0_p axi_ad9361_0/rx_data_in_p
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ad_connect rx_data_in_0_n axi_ad9361_0/rx_data_in_n
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ad_connect tx_clk_out_0_p axi_ad9361_0/tx_clk_out_p
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ad_connect tx_clk_out_0_n axi_ad9361_0/tx_clk_out_n
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ad_connect tx_frame_out_0_p axi_ad9361_0/tx_frame_out_p
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ad_connect tx_frame_out_0_n axi_ad9361_0/tx_frame_out_n
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ad_connect tx_data_out_0_p axi_ad9361_0/tx_data_out_p
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ad_connect tx_data_out_0_n axi_ad9361_0/tx_data_out_n
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ad_connect rx_clk_in_1_p axi_ad9361_1/rx_clk_in_p
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ad_connect rx_clk_in_1_n axi_ad9361_1/rx_clk_in_n
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ad_connect rx_frame_in_1_p axi_ad9361_1/rx_frame_in_p
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ad_connect rx_frame_in_1_n axi_ad9361_1/rx_frame_in_n
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ad_connect rx_data_in_1_p axi_ad9361_1/rx_data_in_p
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ad_connect rx_data_in_1_n axi_ad9361_1/rx_data_in_n
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ad_connect tx_clk_out_1_p axi_ad9361_1/tx_clk_out_p
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ad_connect tx_clk_out_1_n axi_ad9361_1/tx_clk_out_n
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ad_connect tx_frame_out_1_p axi_ad9361_1/tx_frame_out_p
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ad_connect tx_frame_out_1_n axi_ad9361_1/tx_frame_out_n
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ad_connect tx_data_out_1_p axi_ad9361_1/tx_data_out_p
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ad_connect tx_data_out_1_n axi_ad9361_1/tx_data_out_n
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ad_connect axi_ad9361_0/adc_enable_i0 util_adc_pack_0/chan_enable_0
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ad_connect axi_ad9361_0/adc_valid_i0 util_adc_pack_0/chan_valid_0
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ad_connect axi_ad9361_0/adc_data_i0 util_adc_pack_0/chan_data_0
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ad_connect axi_ad9361_0/adc_enable_q0 util_adc_pack_0/chan_enable_1
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ad_connect axi_ad9361_0/adc_valid_q0 util_adc_pack_0/chan_valid_1
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ad_connect axi_ad9361_0/adc_data_q0 util_adc_pack_0/chan_data_1
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ad_connect axi_ad9361_0/adc_enable_i1 util_adc_pack_0/chan_enable_2
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ad_connect axi_ad9361_0/adc_valid_i1 util_adc_pack_0/chan_valid_2
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ad_connect axi_ad9361_0/adc_data_i1 util_adc_pack_0/chan_data_2
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ad_connect axi_ad9361_0/adc_enable_q1 util_adc_pack_0/chan_enable_3
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ad_connect axi_ad9361_0/adc_valid_q1 util_adc_pack_0/chan_valid_3
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ad_connect axi_ad9361_0/adc_data_q1 util_adc_pack_0/chan_data_3
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ad_connect axi_ad9361_1/adc_enable_i0 util_adc_pack_0/chan_enable_4
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ad_connect axi_ad9361_1/adc_valid_i0 util_adc_pack_0/chan_valid_4
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ad_connect axi_ad9361_1/adc_data_i0 util_adc_pack_0/chan_data_4
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ad_connect axi_ad9361_1/adc_enable_q0 util_adc_pack_0/chan_enable_5
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ad_connect axi_ad9361_1/adc_valid_q0 util_adc_pack_0/chan_valid_5
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ad_connect axi_ad9361_1/adc_data_q0 util_adc_pack_0/chan_data_5
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ad_connect axi_ad9361_1/adc_enable_i1 util_adc_pack_0/chan_enable_6
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ad_connect axi_ad9361_1/adc_valid_i1 util_adc_pack_0/chan_valid_6
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ad_connect axi_ad9361_1/adc_data_i1 util_adc_pack_0/chan_data_6
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ad_connect axi_ad9361_1/adc_enable_q1 util_adc_pack_0/chan_enable_7
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ad_connect axi_ad9361_1/adc_valid_q1 util_adc_pack_0/chan_valid_7
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ad_connect axi_ad9361_1/adc_data_q1 util_adc_pack_0/chan_data_7
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ad_connect util_adc_pack_0/dvalid axi_ad9361_adc_dma/fifo_wr_en
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ad_connect util_adc_pack_0/dsync axi_ad9361_adc_dma/fifo_wr_sync
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ad_connect util_adc_pack_0/ddata axi_ad9361_adc_dma/fifo_wr_din
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ad_connect axi_ad9361_0/dac_enable_i0 util_dac_unpack_0/dac_enable_00
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ad_connect axi_ad9361_0/dac_valid_i0 util_dac_unpack_0/dac_valid_00
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ad_connect axi_ad9361_0/dac_data_i0 util_dac_unpack_0/dac_data_00
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ad_connect axi_ad9361_0/dac_enable_q0 util_dac_unpack_0/dac_enable_01
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ad_connect axi_ad9361_0/dac_valid_q0 util_dac_unpack_0/dac_valid_01
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ad_connect axi_ad9361_0/dac_data_q0 util_dac_unpack_0/dac_data_01
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ad_connect axi_ad9361_0/dac_enable_i1 util_dac_unpack_0/dac_enable_02
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ad_connect axi_ad9361_0/dac_valid_i1 util_dac_unpack_0/dac_valid_02
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ad_connect axi_ad9361_0/dac_data_i1 util_dac_unpack_0/dac_data_02
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ad_connect axi_ad9361_0/dac_enable_q1 util_dac_unpack_0/dac_enable_03
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ad_connect axi_ad9361_0/dac_valid_q1 util_dac_unpack_0/dac_valid_03
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ad_connect axi_ad9361_0/dac_data_q1 util_dac_unpack_0/dac_data_03
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ad_connect axi_ad9361_1/dac_enable_i0 util_dac_unpack_0/dac_enable_04
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ad_connect axi_ad9361_1/dac_valid_i0 util_dac_unpack_0/dac_valid_04
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ad_connect axi_ad9361_1/dac_data_i0 util_dac_unpack_0/dac_data_04
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ad_connect axi_ad9361_1/dac_enable_q0 util_dac_unpack_0/dac_enable_05
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ad_connect axi_ad9361_1/dac_valid_q0 util_dac_unpack_0/dac_valid_05
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ad_connect axi_ad9361_1/dac_data_q0 util_dac_unpack_0/dac_data_05
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ad_connect axi_ad9361_1/dac_enable_i1 util_dac_unpack_0/dac_enable_06
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ad_connect axi_ad9361_1/dac_valid_i1 util_dac_unpack_0/dac_valid_06
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ad_connect axi_ad9361_1/dac_data_i1 util_dac_unpack_0/dac_data_06
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ad_connect axi_ad9361_1/dac_enable_q1 util_dac_unpack_0/dac_enable_07
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ad_connect axi_ad9361_1/dac_valid_q1 util_dac_unpack_0/dac_valid_07
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ad_connect axi_ad9361_1/dac_data_q1 util_dac_unpack_0/dac_data_07
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ad_connect util_dac_unpack_0/dma_rd axi_ad9361_dac_dma/fifo_rd_en
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ad_connect util_dac_unpack_0/dma_data axi_ad9361_dac_dma/fifo_rd_dout
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ad_connect util_dac_unpack_0/fifo_valid axi_ad9361_dac_dma/fifo_rd_valid
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ad_connect axi_ad9361_0/adc_dovf axi_ad9361_adc_dma/fifo_wr_overflow
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ad_connect axi_ad9361_0/dac_dunf axi_ad9361_dac_dma/fifo_rd_underflow
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ad_connect constant_32bit/dout axi_ad9361_0/up_dac_gpio_in
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ad_connect constant_32bit/dout axi_ad9361_0/up_adc_gpio_in
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ad_connect constant_32bit/dout axi_ad9361_1/up_dac_gpio_in
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ad_connect constant_32bit/dout axi_ad9361_1/up_adc_gpio_in
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ad_connect constant_1bit/dout axi_ad9361_0/dac_dovf
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ad_connect constant_1bit/dout axi_ad9361_0/adc_dunf
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ad_connect constant_1bit/dout axi_ad9361_1/dac_dovf
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ad_connect constant_1bit/dout axi_ad9361_1/dac_dunf
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ad_connect constant_1bit/dout axi_ad9361_1/adc_dunf
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ad_connect constant_1bit/dout axi_ad9361_1/adc_dovf
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2014-05-19 17:49:49 +00:00
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# address map
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2015-03-25 15:42:11 +00:00
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ad_cpu_interconnect 0x79020000 axi_ad9361_0
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ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma
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ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma
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ad_cpu_interconnect 0x79040000 axi_ad9361_1
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2015-03-31 14:42:44 +00:00
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ad_mem_hp2_interconnect sys_dma_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_dma_clk axi_ad9361_adc_dma/m_dest_axi
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ad_mem_hp3_interconnect sys_dma_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect sys_dma_clk axi_ad9361_dac_dma/m_src_axi
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2014-05-19 17:49:49 +00:00
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2015-03-25 15:42:11 +00:00
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# interrupts
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2014-05-19 17:49:49 +00:00
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2015-03-25 15:42:11 +00:00
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ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
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ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq
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