zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/projects/common/zcu102/zcu102_system_bd.tcl

159 lines
5.9 KiB
Tcl
Raw Normal View History

zcu102: zynq ultrascale
2016-05-03 19:59:20 +00:00
# create board design
# default ports
zcu102- updates
2016-05-10 19:40:32 +00:00
create_bd_port -dir O -from 2 -to 0 spi0_csn
create_bd_port -dir O spi0_sclk
create_bd_port -dir O spi0_mosi
create_bd_port -dir I spi0_miso
create_bd_port -dir O -from 2 -to 0 spi1_csn
create_bd_port -dir O spi1_sclk
create_bd_port -dir O spi1_mosi
create_bd_port -dir I spi1_miso
common/zcu102- spi connections & clock
2016-10-05 18:01:59 +00:00
create_bd_port -dir I -from 94 -to 0 gpio_i
create_bd_port -dir O -from 94 -to 0 gpio_o
common/zcu102: Add gpio_t connections
2017-08-18 13:05:48 +00:00
create_bd_port -dir O -from 94 -to 0 gpio_t
zcu102: zynq ultrascale
2016-05-03 19:59:20 +00:00
zcu102- updates
2016-05-10 19:40:32 +00:00
# instance: sys_ps8
zcu102: Automatic IP version update
2017-05-02 09:30:00 +00:00
ad_ip_instance zynq_ultra_ps_e sys_ps8
zcu102- 2016.4 updates
2017-05-18 18:17:20 +00:00
apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e \
-config {apply_board_preset 1} [get_bd_cells sys_ps8]
zcu102- updates
2016-05-10 19:40:32 +00:00
zcu102- 2016.4 updates
2017-05-18 18:17:20 +00:00
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP0 0
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP1 0
zcu102: Automatic IP version update fix
2017-05-02 09:52:43 +00:00
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP2 1
ad_ip_parameter sys_ps8 CONFIG.PSU__MAXIGP2__DATA_WIDTH 32
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL0_ENABLE 1
zcu102- 2016.4 updates
2017-05-18 18:17:20 +00:00
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL}
common/zcu102: Fix ps8 ref clock 0 frequency assignament
2017-08-18 13:09:18 +00:00
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ 100
zcu102: Automatic IP version update fix
2017-05-02 09:52:43 +00:00
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL1_ENABLE 1
common: Define three global clock nets For all the Xilinx base design, define three global clock nets, which are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk and $sys_iodelay_clk. These clock nets are connected to different clock sources depending of the FPGA architecture used on the carrier. In general the following frequencies are used: - sys_cpu_clk - 100MHz - sys_dma_clk - 200MHz or 250Mhz - sys_iodelay_clk - 200MHz or 500Mhz
2019-05-27 09:52:27 +00:00
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
zcu102- 2016.4 updates
2017-05-18 18:17:20 +00:00
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL}
common: Define three global clock nets For all the Xilinx base design, define three global clock nets, which are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk and $sys_iodelay_clk. These clock nets are connected to different clock sources depending of the FPGA architecture used on the carrier. In general the following frequencies are used: - sys_cpu_clk - 100MHz - sys_dma_clk - 200MHz or 250Mhz - sys_iodelay_clk - 200MHz or 500Mhz
2019-05-27 09:52:27 +00:00
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ 250
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 500
zcu102: Automatic IP version update fix
2017-05-02 09:52:43 +00:00
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ0 1
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ1 1
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE 1
zcu102- updates
2016-05-10 19:40:32 +00:00
zcu102- 2016.4 updates
2017-05-18 18:17:20 +00:00
set_property -dict [list \
CONFIG.PSU__SPI0__PERIPHERAL__ENABLE 1 \
zcu102- updates
2016-05-10 19:40:32 +00:00
CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \
zcu102- 2016.4 updates
2017-05-18 18:17:20 +00:00
CONFIG.PSU__SPI0__GRP_SS1__ENABLE 1 \
CONFIG.PSU__SPI0__GRP_SS2__ENABLE 1 \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ 100 \
CONFIG.PSU__SPI1__PERIPHERAL__ENABLE 1 \
CONFIG.PSU__SPI1__PERIPHERAL__IO EMIO \
CONFIG.PSU__SPI1__GRP_SS1__ENABLE 1 \
CONFIG.PSU__SPI1__GRP_SS2__ENABLE 1 \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ 100 \
zcu102: Automatic IP version update
2017-05-02 09:30:00 +00:00
] [get_bd_cells sys_ps8]
common/zcu102- spi connections & clock
2016-10-05 18:01:59 +00:00
base: Add system_processor_rst for all the global clocks
2019-05-29 06:16:36 +00:00
# processor system reset instances for all the three system clocks
zcu102: Automatic IP version update
2017-05-02 09:30:00 +00:00
ad_ip_instance proc_sys_reset sys_rstgen
ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
base: Add system_processor_rst for all the global clocks
2019-05-29 06:16:36 +00:00
ad_ip_instance proc_sys_reset sys_250m_rstgen
ad_ip_parameter sys_250m_rstgen CONFIG.C_EXT_RST_WIDTH 1
ad_ip_instance proc_sys_reset sys_500m_rstgen
ad_ip_parameter sys_500m_rstgen CONFIG.C_EXT_RST_WIDTH 1
zcu102: zynq ultrascale
2016-05-03 19:59:20 +00:00
zcu102- updates
2016-05-10 19:40:32 +00:00
# system reset/clock definitions
ad_connect sys_cpu_clk sys_ps8/pl_clk0
common: Define three global clock nets For all the Xilinx base design, define three global clock nets, which are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk and $sys_iodelay_clk. These clock nets are connected to different clock sources depending of the FPGA architecture used on the carrier. In general the following frequencies are used: - sys_cpu_clk - 100MHz - sys_dma_clk - 200MHz or 250Mhz - sys_iodelay_clk - 200MHz or 500Mhz
2019-05-27 09:52:27 +00:00
ad_connect sys_250m_clk sys_ps8/pl_clk1
ad_connect sys_500m_clk sys_ps8/pl_clk2
zcu102: zynq ultrascale
2016-05-03 19:59:20 +00:00
base: Add system_processor_rst for all the global clocks
2019-05-29 06:16:36 +00:00
ad_connect sys_ps8/pl_resetn0 sys_rstgen/ext_reset_in
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect sys_ps8/pl_resetn0 sys_250m_rstgen/ext_reset_in
ad_connect sys_250m_clk sys_250m_rstgen/slowest_sync_clk
ad_connect sys_ps8/pl_resetn0 sys_500m_rstgen/ext_reset_in
ad_connect sys_500m_clk sys_500m_rstgen/slowest_sync_clk
common: Define three global clock nets For all the Xilinx base design, define three global clock nets, which are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk and $sys_iodelay_clk. These clock nets are connected to different clock sources depending of the FPGA architecture used on the carrier. In general the following frequencies are used: - sys_cpu_clk - 100MHz - sys_dma_clk - 200MHz or 250Mhz - sys_iodelay_clk - 200MHz or 500Mhz
2019-05-27 09:52:27 +00:00
base: Add system_processor_rst for all the global clocks
2019-05-29 06:16:36 +00:00
ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
ad_connect sys_250m_reset sys_250m_rstgen/peripheral_reset
ad_connect sys_250m_resetn sys_250m_rstgen/peripheral_aresetn
ad_connect sys_500m_reset sys_500m_rstgen/peripheral_reset
ad_connect sys_500m_resetn sys_500m_rstgen/peripheral_aresetn
# generic system clocks&resets pointers
set sys_cpu_clk [get_bd_nets sys_cpu_clk]
set sys_dma_clk [get_bd_nets sys_250m_clk]
set sys_iodelay_clk [get_bd_nets sys_500m_clk]
set sys_cpu_reset [get_bd_nets sys_cpu_reset]
set sys_cpu_resetn [get_bd_nets sys_cpu_resetn]
set sys_dma_reset [get_bd_nets sys_250m_reset]
set sys_dma_resetn [get_bd_nets sys_250m_resetn]
set sys_iodelay_reset [get_bd_nets sys_500m_reset]
set sys_iodelay_resetn [get_bd_nets sys_500m_resetn]
common: Define three global clock nets For all the Xilinx base design, define three global clock nets, which are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk and $sys_iodelay_clk. These clock nets are connected to different clock sources depending of the FPGA architecture used on the carrier. In general the following frequencies are used: - sys_cpu_clk - 100MHz - sys_dma_clk - 200MHz or 250Mhz - sys_iodelay_clk - 200MHz or 500Mhz
2019-05-27 09:52:27 +00:00
zcu102- updates
2016-05-10 19:40:32 +00:00
# gpio
zcu102: zynq ultrascale
2016-05-03 19:59:20 +00:00
zcu102- updates
2016-05-10 19:40:32 +00:00
ad_connect gpio_i sys_ps8/emio_gpio_i
ad_connect gpio_o sys_ps8/emio_gpio_o
common/zcu102: Add gpio_t connections
2017-08-18 13:05:48 +00:00
ad_connect gpio_t sys_ps8/emio_gpio_t
zcu102: zynq ultrascale
2016-05-03 19:59:20 +00:00
zcu102- updates
2016-05-10 19:40:32 +00:00
# spi
zcu102: zynq ultrascale
2016-05-03 19:59:20 +00:00
ZCU102: SPI assign chip selects individually Otherwise, Vivado 2016.4 sets all of the CSNs equal to CSN0. This fix is needed to get the FMCOMMS5 working properly on the ZCU102 (#36)
2017-07-21 08:22:10 +00:00
ad_ip_instance xlconcat spi0_csn_concat
ad_ip_parameter spi0_csn_concat CONFIG.NUM_PORTS 3
ad_connect sys_ps8/emio_spi0_ss_o_n spi0_csn_concat/In0
ad_connect sys_ps8/emio_spi0_ss1_o_n spi0_csn_concat/In1
ad_connect sys_ps8/emio_spi0_ss2_o_n spi0_csn_concat/In2
ad_connect spi0_csn_concat/dout spi0_csn
common/zcu102- spi connections & clock
2016-10-05 18:01:59 +00:00
ad_connect sys_ps8/emio_spi0_sclk_o spi0_sclk
ad_connect sys_ps8/emio_spi0_m_o spi0_mosi
ad_connect sys_ps8/emio_spi0_m_i spi0_miso
zcu102- updates
2016-05-10 19:40:32 +00:00
ad_connect sys_ps8/emio_spi0_ss_i_n VCC
common/zcu102- spi connections & clock
2016-10-05 18:01:59 +00:00
ad_connect sys_ps8/emio_spi0_sclk_i GND
ad_connect sys_ps8/emio_spi0_s_i GND
zcu102: zynq ultrascale
2016-05-03 19:59:20 +00:00
ZCU102: SPI assign chip selects individually Otherwise, Vivado 2016.4 sets all of the CSNs equal to CSN0. This fix is needed to get the FMCOMMS5 working properly on the ZCU102 (#36)
2017-07-21 08:22:10 +00:00
ad_ip_instance xlconcat spi1_csn_concat
ad_ip_parameter spi1_csn_concat CONFIG.NUM_PORTS 3
ad_connect sys_ps8/emio_spi1_ss_o_n spi1_csn_concat/In0
ad_connect sys_ps8/emio_spi1_ss1_o_n spi1_csn_concat/In1
ad_connect sys_ps8/emio_spi1_ss2_o_n spi1_csn_concat/In2
ad_connect spi1_csn_concat/dout spi1_csn
common/zcu102- spi connections & clock
2016-10-05 18:01:59 +00:00
ad_connect sys_ps8/emio_spi1_sclk_o spi1_sclk
ad_connect sys_ps8/emio_spi1_m_o spi1_mosi
ad_connect sys_ps8/emio_spi1_m_i spi1_miso
zcu102- updates
2016-05-10 19:40:32 +00:00
ad_connect sys_ps8/emio_spi1_ss_i_n VCC
common/zcu102- spi connections & clock
2016-10-05 18:01:59 +00:00
ad_connect sys_ps8/emio_spi1_sclk_i GND
ad_connect sys_ps8/emio_spi1_s_i GND
zcu102: zynq ultrascale
2016-05-03 19:59:20 +00:00
# interrupts
zcu102: Automatic IP version update
2017-05-02 09:30:00 +00:00
ad_ip_instance xlconcat sys_concat_intc_0
ad_ip_parameter sys_concat_intc_0 CONFIG.NUM_PORTS 8
zcu102- updates
2016-05-10 19:40:32 +00:00
zcu102: Automatic IP version update
2017-05-02 09:30:00 +00:00
ad_ip_instance xlconcat sys_concat_intc_1
ad_ip_parameter sys_concat_intc_1 CONFIG.NUM_PORTS 8
zcu102- updates
2016-05-10 19:40:32 +00:00
ad_connect sys_concat_intc_0/dout sys_ps8/pl_ps_irq0
ad_connect sys_concat_intc_1/dout sys_ps8/pl_ps_irq1
Remove interrupts from system_top for all xilinx projects - remove interrupts from system_top - for all suported carriers: - remove all interrupt bd pins - connect to GND all initial unconnected interrupt pins - update ad_cpu_interrupt procedure to disconnect a interrupt from GND before connectiong it to another pin.
2018-07-20 15:15:38 +00:00
ad_connect sys_concat_intc_1/In7 GND
ad_connect sys_concat_intc_1/In6 GND
ad_connect sys_concat_intc_1/In5 GND
ad_connect sys_concat_intc_1/In4 GND
ad_connect sys_concat_intc_1/In3 GND
ad_connect sys_concat_intc_1/In2 GND
ad_connect sys_concat_intc_1/In1 GND
ad_connect sys_concat_intc_1/In0 GND
ad_connect sys_concat_intc_0/In7 GND
ad_connect sys_concat_intc_0/In6 GND
ad_connect sys_concat_intc_0/In5 GND
ad_connect sys_concat_intc_0/In4 GND
ad_connect sys_concat_intc_0/In3 GND
ad_connect sys_concat_intc_0/In2 GND
ad_connect sys_concat_intc_0/In1 GND
ad_connect sys_concat_intc_0/In0 GND
zcu102: zynq ultrascale
2016-05-03 19:59:20 +00:00