pluto_hdl_adi/projects/fmcadc2/vc707/system_bd.tcl


## FIFO depth is 16Mb - 1M samples
set adc_fifo_address_width 18

## NOTE: With this configuration the #36Kb BRAM utilization is at ~68%

source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source ../common/fmcadc2_bd.tcl
renamed to match official names 2014-12-08 15:44:15 +00:00
adc\|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb 2018-08-10 07:34:45 +00:00			`## FIFO depth is 16Mb - 1M samples`
projects/system_bd- adc/dac fifo board designs 2017-02-27 21:05:21 +00:00			`set adc_fifo_address_width 18`

adc\|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb 2018-08-10 07:34:45 +00:00			`## NOTE: With this configuration the #36Kb BRAM utilization is at ~68%`

renamed to match official names 2014-12-08 15:44:15 +00:00			`source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl`
file renamed; sed output; fingers crossed 2017-02-22 20:56:37 +00:00			`source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl`
renamed to match official names 2014-12-08 15:44:15 +00:00			`source ../common/fmcadc2_bd.tcl`