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pluto_hdl_adi/projects/ad_fmclidar1_ebz/Makefile

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ad_fmclidar1_ebz: Initial commit This commit was created by squashing the following commits, these messages were kept just for sake of history: ad9694_500ebz: Mirror the SPI interface to FMCB ad9694_500ebz: Set transceiver reference clock to 250 ad9694_500ebz: Allow to configure number of lanes, number of converters and sample rate axi_ad9694: Fix number of lanes, it must be 2 ad9694_500ebz: Update the mirrored spi pin assignments ad9694_500ebz: Gate SPI MISO signals based on chip-select ad9694_500ebz: Set channel pack sample width ad9694_500ebz: Change reference clock location ad9694_500ebz: Remove transceiver memory map arbitration ad9694_500ebz: Ensure ADC FIFO DMA_DATA_WIDTH is not larger ADC_DATA_WIDTH ad9694_500ebz: Adjust breakout board pin locations ad_fmclidar1_ebz: Rename the ad9694_500ebz project ad_fmclidar1_ebz: Fix lane mapping ad_fmclidar1_ebz: Delete deprecated files ad_fmclidar1_ebz: Integrate the axi_laser_driver into the design ad_fmclidar1_ebz: OTW is an active low signal ad_fmclidar1_ebz: zc706: Fix iic_dac signals assignment ad_fmclidar1_ebz: Switch to util_adcfifo ad_fmclidar1_ebz: Enable synced capture for the fifo ad_fmclidar1_ebz/zc706: Enable CAPTURE_TILL_FULL ad_fmclidar1_ebz/zc706: Reduce FIFO size to 2kB ad_fmclidar1_ebz: Laser driver runs on ADC's core clock ad_fmclidar1_ebz_bd: Delete the FIFO instance Because the DMA transfers are going to be relatively small (< 2kbyte), the DMA can handle the data rate, even when the frequency of the laser driver pulse is set to its maximum value. (200 kHz) The synchronization will be done by connecting the generated pulse to the DMA's SYNC input. Although, to support 2 or 1 channel scenarios, we need to use the util_axis_syncgen module to make sure that the DMA catches the pulse, in cases when the pulse width is too narrow. (SYNC is captures when valid and ready is asserted) Also we have to reset the cpack IP before each pulse, to keep the DMA buffer's relative starting point in time fixed, when only 2 or 1 channel is active.
2017-11-10 13:22:16 +00:00
####################################################################################
Makefiles: Update header with the appropriate license
2021-09-15 15:03:11 +00:00
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
ad_fmclidar1_ebz: Initial commit This commit was created by squashing the following commits, these messages were kept just for sake of history: ad9694_500ebz: Mirror the SPI interface to FMCB ad9694_500ebz: Set transceiver reference clock to 250 ad9694_500ebz: Allow to configure number of lanes, number of converters and sample rate axi_ad9694: Fix number of lanes, it must be 2 ad9694_500ebz: Update the mirrored spi pin assignments ad9694_500ebz: Gate SPI MISO signals based on chip-select ad9694_500ebz: Set channel pack sample width ad9694_500ebz: Change reference clock location ad9694_500ebz: Remove transceiver memory map arbitration ad9694_500ebz: Ensure ADC FIFO DMA_DATA_WIDTH is not larger ADC_DATA_WIDTH ad9694_500ebz: Adjust breakout board pin locations ad_fmclidar1_ebz: Rename the ad9694_500ebz project ad_fmclidar1_ebz: Fix lane mapping ad_fmclidar1_ebz: Delete deprecated files ad_fmclidar1_ebz: Integrate the axi_laser_driver into the design ad_fmclidar1_ebz: OTW is an active low signal ad_fmclidar1_ebz: zc706: Fix iic_dac signals assignment ad_fmclidar1_ebz: Switch to util_adcfifo ad_fmclidar1_ebz: Enable synced capture for the fifo ad_fmclidar1_ebz/zc706: Enable CAPTURE_TILL_FULL ad_fmclidar1_ebz/zc706: Reduce FIFO size to 2kB ad_fmclidar1_ebz: Laser driver runs on ADC's core clock ad_fmclidar1_ebz_bd: Delete the FIFO instance Because the DMA transfers are going to be relatively small (< 2kbyte), the DMA can handle the data rate, even when the frequency of the laser driver pulse is set to its maximum value. (200 kHz) The synchronization will be done by connecting the generated pulse to the DMA's SYNC input. Although, to support 2 or 1 channel scenarios, we need to use the util_axis_syncgen module to make sure that the DMA catches the pulse, in cases when the pulse width is too narrow. (SYNC is captures when valid and ready is asserted) Also we have to reset the cpack IP before each pulse, to keep the DMA buffer's relative starting point in time fixed, when only 2 or 1 channel is active.
2017-11-10 13:22:16 +00:00
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk