2015-07-01 16:41:09 +00:00
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# daq3
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create_bd_port -dir I rx_ref_clk
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create_bd_port -dir O rx_sync
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create_bd_port -dir I rx_sysref
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create_bd_port -dir I -from 3 -to 0 rx_data_p
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create_bd_port -dir I -from 3 -to 0 rx_data_n
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create_bd_port -dir I tx_ref_clk
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create_bd_port -dir I tx_sync
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create_bd_port -dir I tx_sysref
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create_bd_port -dir O -from 3 -to 0 tx_data_p
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create_bd_port -dir O -from 3 -to 0 tx_data_n
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create_bd_port -dir O dac_clk
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create_bd_port -dir O dac_valid_0
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create_bd_port -dir O dac_enable_0
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create_bd_port -dir I -from 63 -to 0 dac_ddata_0
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create_bd_port -dir O dac_valid_1
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create_bd_port -dir O dac_enable_1
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create_bd_port -dir I -from 63 -to 0 dac_ddata_1
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create_bd_port -dir I dac_drd
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create_bd_port -dir O -from 127 -to 0 dac_ddata
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create_bd_port -dir O adc_clk
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create_bd_port -dir O adc_enable_0
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create_bd_port -dir O adc_valid_0
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create_bd_port -dir O -from 63 -to 0 adc_data_0
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create_bd_port -dir O adc_enable_1
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create_bd_port -dir O adc_valid_1
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create_bd_port -dir O -from 63 -to 0 adc_data_1
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create_bd_port -dir I adc_dwr
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create_bd_port -dir I adc_dsync
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create_bd_port -dir I -from 127 -to 0 adc_ddata
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# dac peripherals
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set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core]
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set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9152_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9152_jesd
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set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9152_jesd
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set axi_ad9152_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9152_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9152_dma
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set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9152_dma
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# adc peripherals
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set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
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set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9680_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
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set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
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set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
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# dac/adc common gt
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set axi_daq3_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq3_gt]
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set_property -dict [list CONFIG.PCORE_NUM_OF_TX_LANES {4}] $axi_daq3_gt
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set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {4}] $axi_daq3_gt
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set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_0 {0}] $axi_daq3_gt
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set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_1 {3}] $axi_daq3_gt
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set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_2 {1}] $axi_daq3_gt
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set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_3 {2}] $axi_daq3_gt
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# connections (gt)
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ad_connect axi_daq3_gt/ref_clk_q rx_ref_clk
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ad_connect axi_daq3_gt/ref_clk_c tx_ref_clk
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ad_connect axi_daq3_gt/rx_data_p rx_data_p
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ad_connect axi_daq3_gt/rx_data_n rx_data_n
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ad_connect axi_daq3_gt/rx_sync rx_sync
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ad_connect axi_daq3_gt/rx_ext_sysref rx_sysref
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ad_connect axi_daq3_gt/tx_data_p tx_data_p
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ad_connect axi_daq3_gt/tx_data_n tx_data_n
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ad_connect axi_daq3_gt/tx_sync tx_sync
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ad_connect axi_daq3_gt/tx_ext_sysref tx_sysref
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# connections (dac)
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ad_connect axi_daq3_gt/tx_clk_g dac_clk
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ad_connect axi_daq3_gt/tx_clk_g axi_daq3_gt/tx_clk
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ad_connect axi_daq3_gt/tx_clk_g axi_ad9152_core/tx_clk
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ad_connect axi_daq3_gt/tx_clk_g axi_ad9152_jesd/tx_core_clk
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ad_connect axi_daq3_gt/tx_rst axi_ad9152_jesd/tx_reset
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ad_connect axi_daq3_gt/tx_sysref axi_ad9152_jesd/tx_sysref
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create_bd_cell -type ip -vlnv analog.com:user:util_ccat:1.0 util_ccat_tx_gt_charisk
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set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_ccat_tx_gt_charisk]
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set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_ccat_tx_gt_charisk]
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ad_connect util_ccat_tx_gt_charisk/ccat_data axi_daq3_gt/tx_gt_charisk
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ad_connect util_ccat_tx_gt_charisk/data_0 axi_ad9152_jesd/gt0_txcharisk
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ad_connect util_ccat_tx_gt_charisk/data_1 axi_ad9152_jesd/gt1_txcharisk
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ad_connect util_ccat_tx_gt_charisk/data_2 axi_ad9152_jesd/gt2_txcharisk
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ad_connect util_ccat_tx_gt_charisk/data_3 axi_ad9152_jesd/gt3_txcharisk
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create_bd_cell -type ip -vlnv analog.com:user:util_ccat:1.0 util_ccat_tx_gt_data
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set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_ccat_tx_gt_data]
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set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_ccat_tx_gt_data]
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ad_connect util_ccat_tx_gt_data/ccat_data axi_daq3_gt/tx_gt_data
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ad_connect util_ccat_tx_gt_data/data_0 axi_ad9152_jesd/gt0_txdata
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ad_connect util_ccat_tx_gt_data/data_1 axi_ad9152_jesd/gt1_txdata
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ad_connect util_ccat_tx_gt_data/data_2 axi_ad9152_jesd/gt2_txdata
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ad_connect util_ccat_tx_gt_data/data_3 axi_ad9152_jesd/gt3_txdata
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ad_connect axi_daq3_gt/tx_rst_done axi_ad9152_jesd/tx_reset_done
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ad_connect axi_daq3_gt/tx_ip_sync axi_ad9152_jesd/tx_sync
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ad_connect axi_daq3_gt/tx_ip_sof axi_ad9152_jesd/tx_start_of_frame
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ad_connect axi_daq3_gt/tx_ip_data axi_ad9152_jesd/tx_tdata
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ad_connect axi_daq3_gt/tx_data axi_ad9152_core/tx_data
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ad_connect axi_ad9152_core/dac_clk axi_ad9152_dma/fifo_rd_clk
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ad_connect axi_ad9152_core/dac_valid_0 dac_valid_0
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ad_connect axi_ad9152_core/dac_enable_0 dac_enable_0
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ad_connect axi_ad9152_core/dac_ddata_0 dac_ddata_0
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ad_connect axi_ad9152_core/dac_valid_1 dac_valid_1
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ad_connect axi_ad9152_core/dac_enable_1 dac_enable_1
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ad_connect axi_ad9152_core/dac_ddata_1 dac_ddata_1
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ad_connect dac_drd axi_ad9152_dma/fifo_rd_en
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ad_connect dac_ddata axi_ad9152_dma/fifo_rd_dout
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ad_connect axi_ad9152_core/dac_dunf axi_ad9152_dma/fifo_rd_underflow
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ad_connect sys_cpu_resetn axi_ad9152_dma/m_src_axi_aresetn
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# connections (adc)
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ad_connect axi_daq3_gt/rx_clk_g adc_clk
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ad_connect axi_daq3_gt/rx_clk_g axi_daq3_gt/rx_clk
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ad_connect axi_daq3_gt/rx_clk_g axi_ad9680_core/rx_clk
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ad_connect axi_daq3_gt/rx_clk_g axi_ad9680_jesd/rx_core_clk
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ad_connect axi_daq3_gt/rx_rst axi_ad9680_jesd/rx_reset
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ad_connect axi_daq3_gt/rx_sysref axi_ad9680_jesd/rx_sysref
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk
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set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_charisk]
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set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_charisk]
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ad_connect util_bsplit_rx_gt_charisk/data axi_daq3_gt/rx_gt_charisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad9680_jesd/gt0_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_1 axi_ad9680_jesd/gt1_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_2 axi_ad9680_jesd/gt2_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_3 axi_ad9680_jesd/gt3_rxcharisk
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_disperr
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set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_disperr]
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set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_disperr]
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ad_connect util_bsplit_rx_gt_disperr/data axi_daq3_gt/rx_gt_disperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_0 axi_ad9680_jesd/gt0_rxdisperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_1 axi_ad9680_jesd/gt1_rxdisperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_2 axi_ad9680_jesd/gt2_rxdisperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_3 axi_ad9680_jesd/gt3_rxdisperr
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable
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set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_notintable]
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set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_notintable]
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ad_connect util_bsplit_rx_gt_notintable/data axi_daq3_gt/rx_gt_notintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad9680_jesd/gt0_rxnotintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_1 axi_ad9680_jesd/gt1_rxnotintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_2 axi_ad9680_jesd/gt2_rxnotintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_3 axi_ad9680_jesd/gt3_rxnotintable
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data
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set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_bsplit_rx_gt_data]
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set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_data]
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ad_connect util_bsplit_rx_gt_data/data axi_daq3_gt/rx_gt_data
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ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad9680_jesd/gt0_rxdata
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ad_connect util_bsplit_rx_gt_data/split_data_1 axi_ad9680_jesd/gt1_rxdata
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ad_connect util_bsplit_rx_gt_data/split_data_2 axi_ad9680_jesd/gt2_rxdata
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ad_connect util_bsplit_rx_gt_data/split_data_3 axi_ad9680_jesd/gt3_rxdata
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ad_connect axi_daq3_gt/rx_rst_done axi_ad9680_jesd/rx_reset_done
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ad_connect axi_daq3_gt/rx_ip_comma_align axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_daq3_gt/rx_ip_sync axi_ad9680_jesd/rx_sync
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ad_connect axi_daq3_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame
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ad_connect axi_daq3_gt/rx_ip_data axi_ad9680_jesd/rx_tdata
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ad_connect axi_daq3_gt/rx_data axi_ad9680_core/rx_data
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ad_connect axi_ad9680_core/adc_enable_0 adc_enable_0
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ad_connect axi_ad9680_core/adc_valid_0 adc_valid_0
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ad_connect axi_ad9680_core/adc_data_0 adc_data_0
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ad_connect axi_ad9680_core/adc_enable_1 adc_enable_1
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ad_connect axi_ad9680_core/adc_valid_1 adc_valid_1
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ad_connect axi_ad9680_core/adc_data_1 adc_data_1
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ad_connect axi_daq3_gt/rx_rst axi_ad9680_fifo/adc_rst
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ad_connect axi_ad9680_core/adc_clk axi_ad9680_fifo/adc_clk
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ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
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ad_connect adc_dwr axi_ad9680_fifo/adc_wr
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ad_connect adc_ddata axi_ad9680_fifo/adc_wdata
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ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
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ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk
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ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
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ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
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ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
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ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
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ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A60000 axi_daq3_gt
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ad_cpu_interconnect 0x44A00000 axi_ad9152_core
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ad_cpu_interconnect 0x44A90000 axi_ad9152_jesd
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ad_cpu_interconnect 0x7c420000 axi_ad9152_dma
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ad_cpu_interconnect 0x44A10000 axi_ad9680_core
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ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd
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ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
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# gt uses hp3, and 100MHz clock for both DRP and AXI4
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ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect sys_cpu_clk axi_daq3_gt/m_axi
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# interconnect (mem/dac)
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ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect sys_cpu_clk axi_ad9152_dma/m_src_axi
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi
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# interrupts
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ad_cpu_interrupt ps-12 mb-13 axi_ad9152_dma/irq
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ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
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