234 lines
7.9 KiB
Coq
234 lines
7.9 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2021 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// This is the LVDS/DDR interface, note that overrange is independent of data path,
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// software will not be able to relate overrange to a specific sample!
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`timescale 1ns/100ps
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module axi_ltc2387_if #(
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parameter FPGA_TECHNOLOGY = 1,
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parameter IO_DELAY_GROUP = "adc_if_delay_group",
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parameter IODELAY_CTRL = 1,
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parameter DELAY_REFCLK_FREQUENCY = 200,
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parameter [0:0] TWOLANES = 1, // 0 for Single Lane, 1 for Two Lanes
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parameter RESOLUTION = 16 // 16 or 18 bits
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) (
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// delay interface
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input up_clk,
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input [ 1:0] up_dld,
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input [ 9:0] up_dwdata,
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output [ 9:0] up_drdata,
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input delay_clk,
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input delay_rst,
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output delay_locked,
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// adc interface
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input clk,
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input clk_gate,
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input dco_p,
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input dco_n,
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input da_p,
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input da_n,
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input db_p,
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input db_n,
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output adc_valid,
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output reg [RESOLUTION-1:0] adc_data
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);
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localparam ONE_L_WIDTH = (RESOLUTION == 18) ? 9 : 8;
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localparam TWO_L_WIDTH = (RESOLUTION == 18) ? 5 : 4;
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localparam WIDTH = (TWOLANES == 0) ? ONE_L_WIDTH : TWO_L_WIDTH;
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// internal wires
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wire da_p_int_s;
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wire da_n_int_s;
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wire db_p_int_s;
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wire db_n_int_s;
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wire dco;
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wire dco_s;
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wire [17:0] adc_data_int;
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// internal registers
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reg [WIDTH:0] adc_data_da_p = 'b0;
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reg [WIDTH:0] adc_data_da_n = 'b0;
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reg [WIDTH:0] adc_data_db_p = 'b0;
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reg [WIDTH:0] adc_data_db_n = 'b0;
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reg [2:0] clk_gate_d = 'b0;
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// assignments
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assign adc_valid = ~clk_gate_d[2] & clk_gate_d[1];
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always @(posedge clk) begin
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clk_gate_d <= {clk_gate_d[1:0], clk_gate};
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if (clk_gate_d[1] == 1'b1 && clk_gate_d[0] == 1'b0) begin
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if (RESOLUTION == 18) begin
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adc_data <= adc_data_int;
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end else begin
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adc_data <= adc_data_int[15:0];
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end
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end
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end
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always @(posedge dco) begin
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adc_data_da_p <= {adc_data_da_p[WIDTH-1:0], da_p_int_s};
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adc_data_da_n <= {adc_data_da_n[WIDTH-1:0], da_n_int_s};
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adc_data_db_p <= {adc_data_db_p[WIDTH-1:0], db_p_int_s};
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adc_data_db_n <= {adc_data_db_n[WIDTH-1:0], db_n_int_s};
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end
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// bits rearrangement
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if (!TWOLANES) begin
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assign adc_data_int[17] = adc_data_da_p[7];
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assign adc_data_int[16] = adc_data_da_n[7];
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assign adc_data_int[15] = adc_data_da_p[6];
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assign adc_data_int[14] = adc_data_da_n[6];
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assign adc_data_int[13] = adc_data_da_p[5];
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assign adc_data_int[12] = adc_data_da_n[5];
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assign adc_data_int[11] = adc_data_da_p[4];
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assign adc_data_int[10] = adc_data_da_n[4];
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assign adc_data_int[9] = adc_data_da_p[3];
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assign adc_data_int[8] = adc_data_da_n[3];
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assign adc_data_int[7] = adc_data_da_p[2];
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assign adc_data_int[6] = adc_data_da_n[2];
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assign adc_data_int[5] = adc_data_da_p[1];
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assign adc_data_int[4] = adc_data_da_n[1];
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assign adc_data_int[3] = adc_data_da_p[0];
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assign adc_data_int[2] = adc_data_da_n[0];
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assign adc_data_int[1] = da_p_int_s;
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assign adc_data_int[0] = da_n_int_s;
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end else begin
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if (RESOLUTION == 18) begin
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assign adc_data_int[17] = adc_data_da_p[3];
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assign adc_data_int[16] = adc_data_db_p[3];
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assign adc_data_int[15] = adc_data_da_n[3];
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assign adc_data_int[14] = adc_data_db_n[3];
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assign adc_data_int[13] = adc_data_da_p[2];
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assign adc_data_int[12] = adc_data_db_p[2];
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assign adc_data_int[11] = adc_data_da_n[2];
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assign adc_data_int[10] = adc_data_db_n[2];
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assign adc_data_int[9] = adc_data_da_p[1];
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assign adc_data_int[8] = adc_data_db_p[1];
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assign adc_data_int[7] = adc_data_da_n[1];
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assign adc_data_int[6] = adc_data_db_n[1];
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assign adc_data_int[5] = adc_data_da_p[0];
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assign adc_data_int[4] = adc_data_db_p[0];
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assign adc_data_int[3] = adc_data_da_n[0];
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assign adc_data_int[2] = adc_data_db_n[0];
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assign adc_data_int[1] = da_p_int_s;
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assign adc_data_int[0] = db_p_int_s;
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end else begin
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assign adc_data_int[15] = adc_data_da_p[2];
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assign adc_data_int[14] = adc_data_db_p[2];
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assign adc_data_int[13] = adc_data_da_n[2];
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assign adc_data_int[12] = adc_data_db_n[2];
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assign adc_data_int[11] = adc_data_da_p[1];
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assign adc_data_int[10] = adc_data_db_p[1];
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assign adc_data_int[9] = adc_data_da_n[1];
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assign adc_data_int[8] = adc_data_db_n[1];
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assign adc_data_int[7] = adc_data_da_p[0];
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assign adc_data_int[6] = adc_data_db_p[0];
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assign adc_data_int[5] = adc_data_da_n[0];
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assign adc_data_int[4] = adc_data_db_n[0];
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assign adc_data_int[3] = da_p_int_s;
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assign adc_data_int[2] = db_p_int_s;
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assign adc_data_int[1] = da_n_int_s;
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assign adc_data_int[0] = db_n_int_s;
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end
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end
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// data interface - differential to single ended
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ad_data_in #(
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.IDDR_CLK_EDGE("OPPOSITE_EDGE"),
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.IODELAY_CTRL (IODELAY_CTRL),
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.IODELAY_GROUP (IO_DELAY_GROUP),
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.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
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) i_rx_da (
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.rx_clk (dco),
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.rx_data_in_p (da_p),
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.rx_data_in_n (da_n),
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.rx_data_p (da_p_int_s),
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.rx_data_n (da_n_int_s),
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.up_clk (up_clk),
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.up_dld (up_dld[0]),
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.up_dwdata (up_dwdata[4:0]),
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.up_drdata (up_drdata[4:0]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (delay_locked));
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ad_data_in #(
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.IDDR_CLK_EDGE("OPPOSITE_EDGE"),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (IO_DELAY_GROUP),
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.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
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) i_rx_db (
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.rx_clk (dco),
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.rx_data_in_p (db_p),
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.rx_data_in_n (db_n),
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.rx_data_p (db_p_int_s),
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.rx_data_n (db_n_int_s),
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.up_clk (up_clk),
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.up_dld (up_dld[1]),
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.up_dwdata (up_dwdata[9:5]),
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.up_drdata (up_drdata[9:5]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked ());
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// clock
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IBUFGDS i_rx_clk_ibuf (
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.I (dco_p),
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.IB (dco_n),
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.O (dco_s));
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BUFR i_clk_gbuf (
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.CLR (1'b0),
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.CE (1'b1),
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.I (dco_s),
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.O (dco));
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endmodule
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