75 lines
1.6 KiB
VHDL
75 lines
1.6 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.dma_fifo;
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entity axi_streaming_dma_tx_fifo is
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generic (
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RAM_ADDR_WIDTH : integer := 3;
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FIFO_DWIDTH : integer := 32
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);
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port (
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clk : in std_logic;
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resetn : in std_logic;
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fifo_reset : in std_logic;
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-- Enable DMA interface
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enable : in Boolean;
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-- Write port
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S_AXIS_ACLK : in std_logic;
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S_AXIS_TREADY : out std_logic;
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S_AXIS_TDATA : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
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S_AXIS_TLAST : in std_logic;
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S_AXIS_TVALID : in std_logic;
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-- Read port
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out_stb : out std_logic;
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out_ack : in std_logic;
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out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0)
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);
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end;
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architecture imp of axi_streaming_dma_tx_fifo is
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signal in_ack : std_logic;
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signal drain_dma : Boolean;
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begin
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fifo: entity dma_fifo
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generic map (
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RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
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FIFO_DWIDTH => FIFO_DWIDTH
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)
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port map (
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clk => clk,
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resetn => resetn,
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fifo_reset => fifo_reset,
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in_stb => S_AXIS_TVALID,
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in_ack => in_ack,
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in_data => S_AXIS_TDATA,
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out_stb => out_stb,
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out_ack => out_ack,
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out_data => out_data
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);
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drain_process: process (S_AXIS_ACLK) is
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variable enable_d1 : Boolean;
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begin
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if rising_edge(S_AXIS_ACLK) then
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if resetn = '0' then
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drain_dma <= False;
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else
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if S_AXIS_TLAST = '1' then
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drain_dma <= False;
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elsif enable_d1 and enable then
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drain_dma <= True;
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end if;
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enable_d1 := enable;
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end if;
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end if;
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end process;
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S_AXIS_TREADY <= '1' when in_ack = '1' or drain_dma else '0';
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end;
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