2014-02-28 19:26:22 +00:00
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module ad_gt_common_1 (
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// reset and clocks
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rst,
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ref_clk,
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qpll_clk,
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qpll_ref_clk,
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qpll_locked,
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// drp interface
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2015-06-01 17:38:29 +00:00
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up_clk,
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up_drp_sel,
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up_drp_addr,
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up_drp_wr,
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up_drp_wdata,
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up_drp_rdata,
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up_drp_ready,
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up_drp_lanesel,
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up_drp_rxrate);
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2014-02-28 19:26:22 +00:00
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// parameters
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parameter DRP_ID = 0;
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2014-06-05 18:27:18 +00:00
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parameter GTH_GTX_N = 0;
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2014-02-28 19:26:22 +00:00
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parameter QPLL_REFCLK_DIV = 2;
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parameter QPLL_CFG = 27'h06801C1;
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parameter QPLL_FBDIV_RATIO = 1'b1;
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parameter QPLL_FBDIV = 10'b0000110000;
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// reset and clocks
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input rst;
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input ref_clk;
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output qpll_clk;
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output qpll_ref_clk;
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output qpll_locked;
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// drp interface
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2015-06-01 17:38:29 +00:00
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input up_clk;
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input up_drp_sel;
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input [11:0] up_drp_addr;
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input up_drp_wr;
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input [15:0] up_drp_wdata;
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output [15:0] up_drp_rdata;
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output up_drp_ready;
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input [ 7:0] up_drp_lanesel;
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output [ 7:0] up_drp_rxrate;
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2014-02-28 19:26:22 +00:00
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// internal registers
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2015-06-01 17:38:29 +00:00
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reg up_drp_sel_int;
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reg [11:0] up_drp_addr_int;
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reg up_drp_wr_int;
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reg [15:0] up_drp_wdata_int;
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reg [15:0] up_drp_rdata;
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reg up_drp_ready;
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reg [ 7:0] up_drp_rxrate;
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2014-02-28 19:26:22 +00:00
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// internal wires
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2015-06-01 17:38:29 +00:00
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wire [15:0] up_drp_rdata_s;
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wire up_drp_ready_s;
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2014-02-28 19:26:22 +00:00
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// drp control
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2015-06-01 17:38:29 +00:00
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always @(posedge up_clk) begin
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if (up_drp_lanesel == DRP_ID) begin
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up_drp_sel_int <= up_drp_sel;
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up_drp_addr_int <= up_drp_addr;
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up_drp_wr_int <= up_drp_wr;
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up_drp_wdata_int <= up_drp_wdata;
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up_drp_rdata <= up_drp_rdata_s;
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up_drp_ready <= up_drp_ready_s;
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up_drp_rxrate <= 8'hff;
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2014-02-28 19:26:22 +00:00
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end else begin
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2015-06-01 17:38:29 +00:00
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up_drp_sel_int <= 1'd0;
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up_drp_addr_int <= 12'd0;
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up_drp_wr_int <= 1'd0;
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up_drp_wdata_int <= 16'd0;
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up_drp_rdata <= 16'd0;
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up_drp_ready <= 1'd0;
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up_drp_rxrate <= 8'd0;
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2014-02-28 19:26:22 +00:00
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end
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end
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// instantiations
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2014-06-05 18:27:18 +00:00
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generate
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if (GTH_GTX_N == 0) begin
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2014-02-28 19:26:22 +00:00
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GTXE2_COMMON #(
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.SIM_RESET_SPEEDUP ("TRUE"),
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.SIM_QPLLREFCLK_SEL (3'b001),
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.SIM_VERSION ("3.0"),
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.BIAS_CFG (64'h0000040000001000),
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.COMMON_CFG (32'h00000000),
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.QPLL_CFG (QPLL_CFG),
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.QPLL_CLKOUT_CFG (4'b0000),
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.QPLL_COARSE_FREQ_OVRD (6'b010000),
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.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
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.QPLL_CP (10'b0000011111),
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.QPLL_CP_MONITOR_EN (1'b0),
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.QPLL_DMONITOR_SEL (1'b0),
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.QPLL_FBDIV (QPLL_FBDIV),
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.QPLL_FBDIV_MONITOR_EN (1'b0),
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.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
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.QPLL_INIT_CFG (24'h000006),
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.QPLL_LOCK_CFG (16'h21E8),
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.QPLL_LPF (4'b1111),
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.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV))
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i_gtxe2_common (
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2015-06-01 17:38:29 +00:00
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.DRPCLK (up_clk),
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.DRPEN (up_drp_sel_int),
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.DRPADDR (up_drp_addr_int[7:0]),
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.DRPWE (up_drp_wr_int),
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.DRPDI (up_drp_wdata_int),
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.DRPDO (up_drp_rdata_s),
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.DRPRDY (up_drp_ready_s),
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2014-02-28 19:26:22 +00:00
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.GTGREFCLK (1'd0),
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.GTNORTHREFCLK0 (1'd0),
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.GTNORTHREFCLK1 (1'd0),
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.GTREFCLK0 (ref_clk),
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.GTREFCLK1 (1'd0),
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.GTSOUTHREFCLK0 (1'd0),
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.GTSOUTHREFCLK1 (1'd0),
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.QPLLDMONITOR (),
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.QPLLOUTCLK (qpll_clk),
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.QPLLOUTREFCLK (qpll_ref_clk),
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.REFCLKOUTMONITOR (),
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.QPLLFBCLKLOST (),
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.QPLLLOCK (qpll_locked),
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2015-06-01 17:38:29 +00:00
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.QPLLLOCKDETCLK (up_clk),
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2014-02-28 19:26:22 +00:00
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.QPLLLOCKEN (1'd1),
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.QPLLOUTRESET (1'd0),
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.QPLLPD (1'd0),
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.QPLLREFCLKLOST (),
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.QPLLREFCLKSEL (3'b001),
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.QPLLRESET (rst),
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.QPLLRSVD1 (16'b0000000000000000),
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.QPLLRSVD2 (5'b11111),
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.BGBYPASSB (1'd1),
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.BGMONITORENB (1'd1),
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.BGPDB (1'd1),
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.BGRCALOVRD (5'b00000),
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.PMARSVD (8'b00000000),
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.RCALENB (1'd1));
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2014-06-05 18:27:18 +00:00
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end
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if (GTH_GTX_N == 1) begin
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GTHE3_COMMON #(
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.SIM_RESET_SPEEDUP ("TRUE"),
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2015-03-06 17:36:07 +00:00
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.SIM_VERSION (2),
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2014-06-05 18:27:18 +00:00
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.SARC_EN (1'b1),
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.SARC_SEL (1'b0),
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.SDM0_DATA_PIN_SEL (1'b0),
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.SDM0_WIDTH_PIN_SEL (1'b0),
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.SDM1_DATA_PIN_SEL (1'b0),
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.SDM1_WIDTH_PIN_SEL (1'b0),
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.BIAS_CFG0 (16'b0000000000000000),
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.BIAS_CFG1 (16'b0000000000000000),
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.BIAS_CFG2 (16'b0000000000000000),
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.BIAS_CFG3 (16'b0000000001000000),
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.BIAS_CFG4 (16'b0000000000000000),
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.COMMON_CFG0 (16'b0000000000000000),
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.COMMON_CFG1 (16'b0000000000000000),
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.POR_CFG (16'b0000000000000100),
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.QPLL0_CFG0 (16'b0011000000011100),
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.QPLL0_CFG1 (16'b0000000000011000),
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.QPLL0_CFG1_G3 (16'b0000000000011000),
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.QPLL0_CFG2 (16'b0000000001001000),
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.QPLL0_CFG2_G3 (16'b0000000001001000),
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.QPLL0_CFG3 (16'b0000000100100000),
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.QPLL0_CFG4 (16'b0000000000001001),
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.QPLL0_INIT_CFG0 (16'b0000000000000000),
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.QPLL0_LOCK_CFG (16'b0010010111101000),
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.QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
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.QPLL0_SDM_CFG0 (16'b0000000000000000),
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.QPLL0_SDM_CFG1 (16'b0000000000000000),
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.QPLL0_SDM_CFG2 (16'b0000000000000000),
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.QPLL1_CFG0 (16'b0011000000011100),
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.QPLL1_CFG1 (16'b0000000000011000),
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.QPLL1_CFG1_G3 (16'b0000000000011000),
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.QPLL1_CFG2 (16'b0000000001000000),
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.QPLL1_CFG2_G3 (16'b0000000001000000),
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.QPLL1_CFG3 (16'b0000000100100000),
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.QPLL1_CFG4 (16'b0000000000001001),
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.QPLL1_INIT_CFG0 (16'b0000000000000000),
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.QPLL1_LOCK_CFG (16'b0010010111101000),
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.QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
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.QPLL1_SDM_CFG0 (16'b0000000000000000),
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.QPLL1_SDM_CFG1 (16'b0000000000000000),
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.QPLL1_SDM_CFG2 (16'b0000000000000000),
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.RSVD_ATTR0 (16'b0000000000000000),
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.RSVD_ATTR1 (16'b0000000000000000),
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.RSVD_ATTR2 (16'b0000000000000000),
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.RSVD_ATTR3 (16'b0000000000000000),
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.SDM0DATA1_0 (16'b0000000000000000),
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.SDM0INITSEED0_0 (16'b0000000000000000),
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.SDM1DATA1_0 (16'b0000000000000000),
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.SDM1INITSEED0_0 (16'b0000000000000000),
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.RXRECCLKOUT0_SEL (2'b00),
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.RXRECCLKOUT1_SEL (2'b00),
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.QPLL0_INIT_CFG1 (8'b00000000),
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.QPLL1_INIT_CFG1 (8'b00000000),
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.SDM0DATA1_1 (9'b000000000),
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.SDM0INITSEED0_1 (9'b000000000),
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.SDM1DATA1_1 (9'b000000000),
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.SDM1INITSEED0_1 (9'b000000000),
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.BIAS_CFG_RSVD (10'b0000000000),
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.QPLL0_CP (10'b0000011111),
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.QPLL0_CP_G3 (10'b1111111111),
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.QPLL0_LPF (10'b1111111111),
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.QPLL0_LPF_G3 (10'b0000010101),
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.QPLL1_CP (10'b0000011111),
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.QPLL1_CP_G3 (10'b1111111111),
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.QPLL1_LPF (10'b1111111111),
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.QPLL1_LPF_G3 (10'b0000010101),
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.QPLL0_FBDIV (QPLL_FBDIV),
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.QPLL0_FBDIV_G3 (80),
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.QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
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.QPLL1_FBDIV (QPLL_FBDIV),
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.QPLL1_FBDIV_G3 (80),
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.QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV))
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i_gthe3_common (
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.BGBYPASSB (1'd1),
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.BGMONITORENB (1'd1),
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.BGPDB (1'd1),
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.BGRCALOVRD (5'b11111),
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.BGRCALOVRDENB (1'd1),
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2015-06-01 17:38:29 +00:00
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.DRPADDR (up_drp_addr_int[8:0]),
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.DRPCLK (up_clk),
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.DRPDI (up_drp_wdata_int),
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.DRPEN (up_drp_sel_int),
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.DRPWE (up_drp_wr_int),
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2014-06-05 18:27:18 +00:00
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.GTGREFCLK0 (1'd0),
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.GTGREFCLK1 (1'd0),
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.GTNORTHREFCLK00 (1'd0),
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.GTNORTHREFCLK01 (1'd0),
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.GTNORTHREFCLK10 (1'd0),
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.GTNORTHREFCLK11 (1'd0),
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.GTREFCLK00 (ref_clk),
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.GTREFCLK01 (1'd0),
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.GTREFCLK10 (1'd0),
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.GTREFCLK11 (1'd0),
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.GTSOUTHREFCLK00 (1'd0),
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.GTSOUTHREFCLK01 (1'd0),
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.GTSOUTHREFCLK10 (1'd0),
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.GTSOUTHREFCLK11 (1'd0),
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.PMARSVD0 (8'd0),
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.PMARSVD1 (8'd0),
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.QPLLRSVD1 (8'd0),
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.QPLLRSVD2 (5'd0),
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.QPLLRSVD3 (5'd0),
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.QPLLRSVD4 (8'd0),
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.QPLL0CLKRSVD0 (1'd0),
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.QPLL0CLKRSVD1 (1'd0),
|
2015-06-01 17:38:29 +00:00
|
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|
.QPLL0LOCKDETCLK (up_clk),
|
2014-06-05 18:27:18 +00:00
|
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|
.QPLL0LOCKEN (1'd1),
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.QPLL0PD (1'd0),
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.QPLL0REFCLKSEL (3'b001),
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.QPLL0RESET (rst),
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.QPLL1CLKRSVD0 (1'd0),
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.QPLL1CLKRSVD1 (1'd0),
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.QPLL1LOCKDETCLK (1'd0),
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.QPLL1LOCKEN (1'd0),
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|
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.QPLL1PD (1'd1),
|
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|
|
.QPLL1REFCLKSEL (3'b001),
|
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|
.QPLL1RESET (1'd1),
|
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|
|
.RCALENB (1'd1),
|
2015-06-01 17:38:29 +00:00
|
|
|
.DRPDO (up_drp_rdata_s),
|
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|
|
|
.DRPRDY (up_drp_ready_s),
|
2014-06-05 18:27:18 +00:00
|
|
|
.PMARSVDOUT0 (),
|
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|
|
.PMARSVDOUT1 (),
|
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|
|
|
.QPLLDMONITOR0 (),
|
|
|
|
|
.QPLLDMONITOR1 (),
|
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|
|
|
.QPLL0FBCLKLOST (),
|
|
|
|
|
.QPLL0LOCK (qpll_locked),
|
|
|
|
|
.QPLL0OUTCLK (qpll_clk),
|
|
|
|
|
.QPLL0OUTREFCLK (qpll_ref_clk),
|
|
|
|
|
.QPLL0REFCLKLOST (),
|
|
|
|
|
.QPLL1FBCLKLOST (),
|
|
|
|
|
.QPLL1LOCK (),
|
|
|
|
|
.QPLL1OUTCLK (),
|
|
|
|
|
.QPLL1OUTREFCLK (),
|
|
|
|
|
.QPLL1REFCLKLOST (),
|
|
|
|
|
.REFCLKOUTMONITOR0 (),
|
|
|
|
|
.REFCLKOUTMONITOR1 (),
|
|
|
|
|
.RXRECCLK0_SEL (),
|
|
|
|
|
.RXRECCLK1_SEL ());
|
|
|
|
|
end
|
|
|
|
|
endgenerate
|
2014-02-28 19:26:22 +00:00
|
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|
endmodule
|
|
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|
// ***************************************************************************
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|
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|
|
// ***************************************************************************
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|
