81 lines
1.7 KiB
VHDL
81 lines
1.7 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.dma_fifo;
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entity axi_streaming_dma_rx_fifo is
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generic (
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RAM_ADDR_WIDTH : integer := 3;
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FIFO_DWIDTH : integer := 32
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);
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port (
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clk : in std_logic;
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resetn : in std_logic;
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fifo_reset : in std_logic;
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-- Enable DMA interface
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enable : in Boolean;
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period_len : in integer range 0 to 65535;
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-- Read port
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M_AXIS_ACLK : in std_logic;
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M_AXIS_TREADY : in std_logic;
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M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
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M_AXIS_TLAST : out std_logic;
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M_AXIS_TVALID : out std_logic;
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M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
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-- Write port
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in_stb : in std_logic;
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in_ack : out std_logic;
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in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0)
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);
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end;
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architecture imp of axi_streaming_dma_rx_fifo is
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signal out_stb : std_logic;
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signal period_count : integer range 0 to 65535;
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signal last : std_logic;
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begin
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M_AXIS_TVALID <= out_stb;
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fifo: entity dma_fifo
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generic map (
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RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
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FIFO_DWIDTH => FIFO_DWIDTH
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)
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port map (
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clk => clk,
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resetn => resetn,
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fifo_reset => fifo_reset,
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in_stb => in_stb,
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in_ack => in_ack,
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in_data => in_data,
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out_stb => out_stb,
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out_ack => M_AXIS_TREADY,
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out_data => M_AXIS_TDATA
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);
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M_AXIS_TKEEP <= "1111";
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M_AXIS_TLAST <= '1' when period_count = 0 else '0';
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period_counter: process(M_AXIS_ACLK) is
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begin
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if resetn = '0' then
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period_count <= period_len;
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else
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if out_stb = '1' and M_AXIS_TREADY = '1' then
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if period_count = 0 then
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period_count <= period_len;
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else
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period_count <= period_count - 1;
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end if;
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end if;
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end if;
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end process;
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end;
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