196 lines
4.5 KiB
Plaintext
196 lines
4.5 KiB
Plaintext
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TITLE
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Base (common to all cores)
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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0x0000
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REG_VERSION
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Version and Scratch Registers
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ENDREG
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FIELD
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[31:0] 0x00000000
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VERSION[31:0]
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RO
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Version number. Unique to all cores.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0001
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REG_ID
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Version and Scratch Registers
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ENDREG
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FIELD
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[31:0] 0x00000000
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ID[31:0]
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RO
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Instance identifier number.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0002
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REG_SCRATCH
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Version and Scratch Registers
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ENDREG
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FIELD
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[31:0] 0x00000000
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SCRATCH[31:0]
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RW
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Scratch register.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0003
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REG_CONFIG
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Version and Scratch Registers
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ENDREG
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FIELD
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[0] 0x0
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IQCORRECTION_DISABLE
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RO
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If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)
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ENDFIELD
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FIELD
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[1] 0x0
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DCFILTER_DISABLE
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RO
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If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)
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ENDFIELD
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FIELD
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[2] 0x0
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DATAFORMAT_DISABLE
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RO
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If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)
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ENDFIELD
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FIELD
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[3] 0x0
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USERPORTS_DISABLE
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RO
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If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)
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ENDFIELD
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FIELD
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[4] 0x0
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MODE_1R1T
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RO
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If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)
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ENDFIELD
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FIELD
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[5] 0x0
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DELAY_CONTROL_DISABLE
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RO
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If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)
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ENDFIELD
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FIELD
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[6] 0x0
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DDS_DISABLE
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RO
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If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)
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ENDFIELD
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FIELD
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[7] 0x0
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CMOS_OR_LVDS_N
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RO
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CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)
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ENDFIELD
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FIELD
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[8] 0x0
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PPS_RECEIVER_ENABLE
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RO
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If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)
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ENDFIELD
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FIELD
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[9] 0x0
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SCALECORRECTION_ONLY
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RO
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If set, indicates that the IQ Correction module implements only scale correction.
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IQ correction must be enabled. (as a result of a configuration of the IP instance)
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ENDFIELD
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FIELD
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[12] 0x0
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EXT_SYNC
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RO
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If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0004
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REG_PPS_IRQ_MASK
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PPS Interrupt mask
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ENDREG
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FIELD
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[0] 0x1
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PPS_IRQ_MASK
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RW
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Mask bit for the 1PPS receiver interrupt
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0007
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REG_FPGA_INFO
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FPGA device information [[https://github.com/analogdevicesinc/hdl/blob/master/library/scripts/adi_intel_device_info_enc.tcl |Intel encoded values]]
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[[https://github.com/analogdevicesinc/hdl/blob/master/library/scripts/adi_xilinx_device_info_enc.tcl |Xilinx encoded values]]
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ENDREG
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FIELD
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[31:24] 0x0
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FPGA_TECHNOLOGY
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RO
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Encoded value describing the technology/generation of the FPGA device (arria 10/7series)
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ENDFIELD
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FIELD
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[23:16] 0x0
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FPGA_FAMILY
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RO
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Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)
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ENDFIELD
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FIELD
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[15:8] 0x0
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SPEED_GRADE
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RO
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Encoded value describing the FPGA's speed-grade
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ENDFIELD
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FIELD
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[7:0] 0x0
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DEV_PACKAGE
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RO
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Encoded value describing the device package. The package might affect high-speed interfaces
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ENDFIELD
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############################################################################################
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############################################################################################
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