135 lines
2.8 KiB
Plaintext
135 lines
2.8 KiB
Plaintext
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TITLE
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General Purpose Registers (axi_gpreg)
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AXI_GPREG
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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0x0100
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REG_IO_ENB
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IO control register
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ENDREG
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FIELD
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[31:0] 0x00000000
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IO_ENB
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RW
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IO control register (use as tri-state control, logic depends on the buffer type).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0101
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REG_IO_OUT
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IO output register
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ENDREG
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FIELD
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[31:0] 0x00000000
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IO_ENB
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RW
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IO output register.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0102
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REG_IO_IN
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IO input register
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ENDREG
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FIELD
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[31:0] 0x00000000
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IO_IN
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RO
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IO input register.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0110
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REG_*
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Channel 1, similar to register 0x100 to 0x10f.
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ENDREG
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REG
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0x0120
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REG_*
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Channel 2, similar to register 0x100 to 0x10f.
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ENDREG
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REG
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0x01f0
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REG_*
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Channel 15, similar to register 0x100 to 0x10f.
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ENDREG
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############################################################################################
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############################################################################################
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REG
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0x0200
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REG_CM_RESET
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Reset register
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ENDREG
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FIELD
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[0] 0x0
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CM_RESET_N
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RW
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Reset register (write a 0x01 to bring core out of reset).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0202
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REG_CM_COUNT
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Clock count register
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ENDREG
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FIELD
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[31:0] 0x00000000
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CM_CLK_COUNT
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RO
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Interface clock frequency. This is relative to the processor clock and in many cases is
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100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
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clock the minimum is 1.523kHz and maximum is 6.554THz.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0210
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REG_*
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Channel 1, similar to register 0x200 to 0x20f.
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ENDREG
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REG
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0x0220
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REG_*
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Channel 2, similar to register 0x200 to 0x20f.
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ENDREG
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REG
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0x02f0
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REG_*
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Channel 15, similar to register 0x200 to 0x20f.
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ENDREG
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############################################################################################
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############################################################################################
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