pluto_hdl_adi/library/jesd204/tb/frame_align_tb.v

//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary.  If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact jesd204-licensing@analog.com for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//

`timescale 1ns/100ps

module frame_align_tb;
  parameter VCD_FILE = "frame_align_tb.vcd";
  parameter NUM_LANES = 4;
  parameter NUM_LINKS = 1;
  parameter OCTETS_PER_FRAME = 3;
  parameter FRAMES_PER_MULTIFRAME = 8;
  parameter NUM_CONVERTERS = 1;
  parameter N = 16;
  parameter NP = 16;
  parameter HIGH_DENSITY = 1'b0;
  parameter ENABLE_SCRAMBLER = 0;
  parameter BUFFER_EARLY_RELEASE = 1;
  parameter SYSREF_DISABLE = 1;
  parameter SYSREF_ONE_SHOT = 0;
  parameter LANE_DELAY = 1;
  parameter DATA_PATH_WIDTH = 8;
  parameter DATA_RANDOM = ENABLE_SCRAMBLER ? 0 : 1;
  parameter ALIGN_ERROR_PERCENT = 50;

  localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
  localparam BEATS_PER_MULTIFRAME = OCTETS_PER_FRAME * FRAMES_PER_MULTIFRAME / 4;
  localparam TX_LATENCY = 3;
  wire [31:0] RX_LATENCY = 3 + i_rx.CHAR_INFO_REGISTERED + i_rx.ALIGN_MUX_REGISTERED + i_rx.SCRAMBLER_REGISTERED;
  wire [31:0] BASE_LATENCY = TX_LATENCY + RX_LATENCY;
  localparam SYSREF_HALF_COUNT = OCTETS_PER_FRAME * FRAMES_PER_MULTIFRAME;

  `define TIMEOUT 1000000

  `include "tb_base.v"

  reg [5:0] tx_counter = 'h00;
  reg [5:0] rx_counter = 'h00;
  reg [NUM_LANES*DATA_PATH_WIDTH*8-1:0] rx_mask = 64'hffffffffffff0000;
  wire tx_ready;
  wire rx_valid;
  wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] rx_data;
  wire [DATA_PATH_WIDTH-1:0] rx_eof;
  wire [DATA_PATH_WIDTH-1:0] rx_sof;
  wire cur_data_mismatch;
  reg data_mismatch = 1'b1;
  wire [NUM_LINKS-1:0] sync;

  always @(posedge clk) begin
    if (sync == 1'b0) begin
      tx_counter <= 'h00000000;
    end else if (tx_ready == 1'b1) begin
      tx_counter <= tx_counter + 1'b1;
    end
  end

  always @(posedge clk) begin
    if (sync == 1'b0) begin
      rx_counter <= 'h00000000;
      if (ENABLE_SCRAMBLER == 1'b1) begin
        rx_mask <= {NUM_LANES{64'hffffffffffff0000}}; // First two octets are invalid due to scrambling
      end else begin
        rx_mask <= {NUM_LANES{64'hffffffffffffffff}};
      end
    end else if (rx_valid == 1'b1) begin
      rx_counter <= rx_counter + 1'b1;
      rx_mask <= {NUM_LANES{64'hffffffffffffffff}};
    end
  end

  reg  [(DATA_PATH_WIDTH*8)-1:0] tx_random_data;
  wire [(DATA_PATH_WIDTH*8)-1:0] tx_data;
  wire [(DATA_PATH_WIDTH*8)-1:0] rx_ref_data;

  genvar ii;
  generate
  for(ii = 0; ii < DATA_PATH_WIDTH; ii=ii+1) begin : data_gen
    wire [1:0] ii_sig = ii;

    always @(posedge clk) begin
      tx_random_data[ii*8+:8] <= $urandom();
    end

    assign tx_data[ii*8+:8] = DATA_RANDOM ? tx_random_data[ii*8+:8] : {tx_counter, ii_sig};
    assign rx_ref_data[ii*8+:8] = {rx_counter, ii_sig};
  end
  endgenerate

  wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] phy_data_out;
  wire [NUM_LANES*DATA_PATH_WIDTH-1:0] phy_charisk_out;
  wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] phy_data_delayed;
  wire [NUM_LANES*DATA_PATH_WIDTH-1:0] phy_charisk_delayed;
  reg  [NUM_LANES*DATA_PATH_WIDTH*8-1:0] phy_data_in;
  reg  [NUM_LANES*DATA_PATH_WIDTH-1:0] phy_charisk_in;

  reg align_err_mf;
  reg align_err_f;
  reg cur_err;

  reg [9:0] sysref_counter = 'h00;
  reg sysref_rx = 1'b0;
  reg sysref_tx = 1'b0;

  always @(posedge clk) begin
    if (sysref_counter == (SYSREF_HALF_COUNT-1)) begin
      sysref_rx <= ~sysref_rx;
      sysref_counter <= 'b0;
    end else begin
    sysref_counter <= sysref_counter + 1'b1;
    end
    sysref_tx <= sysref_rx;
  end

  localparam MAX_LANE_DELAY = LANE_DELAY + NUM_LANES;

  reg [10:0] phy_delay_fifo_wr;
  reg [DATA_PATH_WIDTH*9*NUM_LANES-1:0] phy_delay_fifo[0:MAX_LANE_DELAY-1];

  always @(posedge clk) begin
    phy_delay_fifo[phy_delay_fifo_wr] <= {phy_charisk_out,phy_data_out};

    if (reset == 1'b1 || phy_delay_fifo_wr == MAX_LANE_DELAY-1) begin
      phy_delay_fifo_wr <= 'h00;
    end else begin
      phy_delay_fifo_wr <= phy_delay_fifo_wr + 1'b1;
    end
  end

  initial begin
    align_err_mf = 1'b0;
    align_err_f = 1'b0;

    #100000;
    align_err_f = 1'b1;
    #50000;
    align_err_f = 1'b0;
    #100000;

    align_err_mf = 1'b1;
    #50000;
    align_err_mf = 1'b0;
    #100000;

    align_err_f = 1'b1;
    align_err_mf = 1'b1;
    #50000;
    align_err_f = 1'b0;
    align_err_mf = 1'b0;
    #100000;
    $finish;
  end

  always @(posedge clk) begin
    if(ALIGN_ERROR_PERCENT != 0) begin
      cur_err <= $urandom_range(99) < ALIGN_ERROR_PERCENT;
    end else begin
      cur_err <= 1'b0;
    end
  end

  genvar i;
  generate for (i = 0; i < NUM_LANES; i = i + 1) begin
    localparam OFF = MAX_LANE_DELAY - (i + LANE_DELAY);
    assign phy_data_delayed[DATA_PATH_WIDTH*8*i+(DATA_PATH_WIDTH*8)-1:DATA_PATH_WIDTH*8*i] =
      phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][DATA_PATH_WIDTH*8*i+(DATA_PATH_WIDTH*8)-1:DATA_PATH_WIDTH*8*i];
    assign phy_charisk_delayed[DATA_PATH_WIDTH*i+DATA_PATH_WIDTH-1:DATA_PATH_WIDTH*i]=
      phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][DATA_PATH_WIDTH*i+DATA_PATH_WIDTH-1+NUM_LANES*DATA_PATH_WIDTH*8:DATA_PATH_WIDTH*i+DATA_PATH_WIDTH*8*NUM_LANES];
  end endgenerate

  always @(*) begin
    phy_data_in = phy_data_delayed;
    phy_charisk_in = phy_charisk_delayed;

    if(cur_err) begin
      if(align_err_mf) begin
        phy_data_in = {NUM_LANES*4{8'h7C}};
        phy_charisk_in = {NUM_LANES*4{1'b1}};
      end else if(align_err_f) begin
        phy_data_in = {NUM_LANES*4{8'hFC}};
        phy_charisk_in = {NUM_LANES*4{1'b1}};
      end
    end
  end


  wire [NUM_LANES-1:0] tx_cfg_lanes_disable;
  wire [NUM_LINKS-1:0] tx_cfg_links_disable;
  wire [9:0] tx_cfg_octets_per_multiframe;
  wire [7:0] tx_cfg_octets_per_frame;
  wire [7:0] tx_cfg_lmfc_offset;
  wire tx_cfg_sysref_disable;
  wire tx_cfg_sysref_oneshot;
  wire tx_cfg_continuous_cgs;
  wire tx_cfg_continuous_ilas;
  wire tx_cfg_skip_ilas;
  wire [7:0] tx_cfg_mframes_per_ilas;
  wire tx_cfg_disable_char_replacement;
  wire tx_cfg_disable_scrambler;
  wire tx_lmfc_edge;
  wire tx_lmfc_clk;
  wire [DATA_PATH_WIDTH-1:0] tx_eof;
  wire [DATA_PATH_WIDTH-1:0] tx_sof;

  wire tx_ilas_config_rd;
  wire [1:0] tx_ilas_config_addr;
  wire [DATA_PATH_WIDTH*8*NUM_LANES-1:0] tx_ilas_config_data;
  wire tx_event_sysref_edge;
  wire tx_event_sysref_alignment_error;
  wire [NUM_LINKS-1:0] tx_status_sync;
  wire [1:0] tx_status_state;

  jesd204_tx_static_config #(
    .NUM_LANES(NUM_LANES),
    .NUM_LINKS(NUM_LINKS),
    .OCTETS_PER_FRAME(OCTETS_PER_FRAME),
    .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME),
    .NUM_CONVERTERS(NUM_CONVERTERS),
    .N(N),
    .NP(NP),
    .HIGH_DENSITY(HIGH_DENSITY),
    .SCR(ENABLE_SCRAMBLER),
    .LINK_MODE(1),
    .SYSREF_DISABLE(SYSREF_DISABLE),
    .SYSREF_ONE_SHOT(SYSREF_ONE_SHOT),
    .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
  ) i_tx_cfg (
    .clk(clk),

    .cfg_lanes_disable(tx_cfg_lanes_disable),
    .cfg_links_disable(tx_cfg_links_disable),
    .cfg_octets_per_multiframe(tx_cfg_octets_per_multiframe),
    .cfg_octets_per_frame(tx_cfg_octets_per_frame),
    .cfg_lmfc_offset(tx_cfg_lmfc_offset),
    .cfg_sysref_disable(tx_cfg_sysref_disable),
    .cfg_sysref_oneshot(tx_cfg_sysref_oneshot),
    .cfg_continuous_cgs(tx_cfg_continuous_cgs),
    .cfg_continuous_ilas(tx_cfg_continuous_ilas),
    .cfg_skip_ilas(tx_cfg_skip_ilas),
    .cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas),
    .cfg_disable_char_replacement(tx_cfg_disable_char_replacement),
    .cfg_disable_scrambler(tx_cfg_disable_scrambler),

    .ilas_config_rd(tx_ilas_config_rd),
    .ilas_config_addr(tx_ilas_config_addr),
    .ilas_config_data(tx_ilas_config_data)
  );

  jesd204_tx #(
    .NUM_LANES(NUM_LANES),
    .NUM_LINKS(NUM_LINKS),
    .NUM_OUTPUT_PIPELINE(0),
    .LINK_MODE(1),
    .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
  ) i_tx (
    .clk(clk),
    .reset(reset),

    .phy_data(phy_data_out),
    .phy_charisk(phy_charisk_out),
    .phy_header(),

    .sysref(sysref_tx),
    .lmfc_edge(tx_lmfc_edge),
    .lmfc_clk(tx_lmfc_clk),

    .sync(sync),

    .tx_data({NUM_LANES{tx_data}}),
    .tx_ready(tx_ready),
    .tx_eof(tx_eof),
    .tx_sof(tx_sof),
    .tx_valid(1'b1),

    .cfg_lanes_disable(tx_cfg_lanes_disable),
    .cfg_links_disable(tx_cfg_links_disable),
    .cfg_octets_per_multiframe(tx_cfg_octets_per_multiframe),
    .cfg_octets_per_frame(tx_cfg_octets_per_frame),
    .cfg_lmfc_offset(tx_cfg_lmfc_offset),
    .cfg_sysref_disable(tx_cfg_sysref_disable),
    .cfg_sysref_oneshot(tx_cfg_sysref_oneshot),
    .cfg_continuous_cgs(tx_cfg_continuous_cgs),
    .cfg_continuous_ilas(tx_cfg_continuous_ilas),
    .cfg_skip_ilas(tx_cfg_skip_ilas),
    .cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas),
    .cfg_disable_char_replacement(tx_cfg_disable_char_replacement),
    .cfg_disable_scrambler(tx_cfg_disable_scrambler),

    .ilas_config_rd(tx_ilas_config_rd),
    .ilas_config_addr(tx_ilas_config_addr),
    .ilas_config_data(tx_ilas_config_data),

    .ctrl_manual_sync_request(1'b0),


    .event_sysref_edge (tx_event_sysref_edge),
    .event_sysref_alignment_error (tx_event_sysref_alignment_error),

    .status_sync (tx_status_sync),
    .status_state (tx_status_state)
  );

  wire [NUM_LANES-1:0] rx_cfg_lanes_disable;
  wire [NUM_LINKS-1:0] rx_cfg_links_disable;
  wire [9:0] rx_cfg_octets_per_multiframe;
  wire [7:0] rx_cfg_octets_per_frame;
  wire [7:0] rx_cfg_lmfc_offset;
  wire rx_cfg_sysref_disable;
  wire rx_cfg_sysref_oneshot;
  wire rx_cfg_disable_scrambler;
  wire rx_cfg_disable_char_replacement;
  wire rx_cfg_buffer_early_release;
  wire [7:0] rx_cfg_buffer_delay;
  wire [NUM_LANES-1:0] rx_status_lane_ifs_ready;
  wire [NUM_LANES*14-1:0] rx_status_lane_latency;
  wire [NUM_LANES*8-1:0] rx_status_lane_frame_align_err_cnt;
  wire [7:0] rx_cfg_frame_align_err_threshold;
  wire [32*NUM_LANES-1:0] rx_status_err_statistics_cnt;
  wire rx_lmfc_edge;
  wire rx_lmfc_clk;
  wire rx_event_sysref_alignment_error;
  wire rx_event_sysref_edge;
  wire [NUM_LANES-1:0] rx_ilas_config_valid;
  wire [NUM_LANES*2-1:0] rx_ilas_config_addr;
  wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] rx_ilas_config_data;
  wire [1:0] rx_status_ctrl_state;
  wire [2*NUM_LANES-1:0] rx_status_lane_cgs_state;
  wire rx_phy_en_char_align;

  jesd204_rx_static_config #(
    .NUM_LANES(NUM_LANES),
    .NUM_LINKS(NUM_LINKS),
    .OCTETS_PER_FRAME(OCTETS_PER_FRAME),
    .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME),
    .SCR(ENABLE_SCRAMBLER),
    .BUFFER_EARLY_RELEASE(BUFFER_EARLY_RELEASE),
    .LINK_MODE(1),
    .SYSREF_DISABLE(SYSREF_DISABLE),
    .SYSREF_ONE_SHOT(SYSREF_ONE_SHOT),
    .DATA_PATH_WIDTH(DATA_PATH_WIDTH)
  ) i_rx_cfg (
    .clk(clk),

    .cfg_lanes_disable(rx_cfg_lanes_disable),
    .cfg_links_disable(rx_cfg_links_disable),
    .cfg_octets_per_multiframe(rx_cfg_octets_per_multiframe),
    .cfg_octets_per_frame(rx_cfg_octets_per_frame),
    .cfg_lmfc_offset(rx_cfg_lmfc_offset),
    .cfg_sysref_disable(rx_cfg_sysref_disable),
    .cfg_sysref_oneshot(rx_cfg_sysref_oneshot),
    .cfg_disable_scrambler(rx_cfg_disable_scrambler),
    .cfg_disable_char_replacement(rx_cfg_disable_char_replacement),
    .cfg_buffer_delay(rx_cfg_buffer_delay),
    .cfg_buffer_early_release(rx_cfg_buffer_early_release),
    .cfg_frame_align_err_threshold(rx_cfg_frame_align_err_threshold)
  );

  jesd204_rx #(
    .NUM_LANES(NUM_LANES),
    .NUM_LINKS(NUM_LINKS),
    .NUM_INPUT_PIPELINE(1),
    .LINK_MODE(1),
    .DATA_PATH_WIDTH(DATA_PATH_WIDTH),
    .ENABLE_FRAME_ALIGN_CHECK(1),
    .ENABLE_FRAME_ALIGN_ERR_RESET(1)
  ) i_rx (
    .clk(clk),
    .reset(reset),

    .phy_data(phy_data_in),
    .phy_header({2*NUM_LANES{1'b0}}),
    .phy_charisk(phy_charisk_in),
    .phy_notintable({NUM_LANES*DATA_PATH_WIDTH{1'b0}}),
    .phy_disperr({NUM_LANES*DATA_PATH_WIDTH{1'b0}}),
    .phy_block_sync({NUM_LANES{1'b0}}),

    .sysref(sysref_rx),
    .lmfc_edge(rx_lmfc_edge),
    .lmfc_clk(rx_lmfc_clk),

    .event_sysref_alignment_error(rx_event_sysref_alignment_error),
    .event_sysref_edge(rx_event_sysref_edge),

    .sync(sync),

    .phy_en_char_align(rx_phy_en_char_align),

    .rx_data(rx_data),
    .rx_valid(rx_valid),
    .rx_eof(rx_eof),
    .rx_sof(rx_sof),

    .cfg_lanes_disable(rx_cfg_lanes_disable),
    .cfg_links_disable(rx_cfg_links_disable),
    .cfg_octets_per_multiframe(rx_cfg_octets_per_multiframe),
    .cfg_octets_per_frame(rx_cfg_octets_per_frame),
    .cfg_lmfc_offset(rx_cfg_lmfc_offset),
    .cfg_sysref_disable(rx_cfg_sysref_disable),
    .cfg_sysref_oneshot(rx_cfg_sysref_oneshot),
    .cfg_buffer_early_release(rx_cfg_buffer_early_release),
    .cfg_buffer_delay(rx_cfg_buffer_delay),
    .cfg_disable_char_replacement(rx_cfg_disable_char_replacement),
    .cfg_disable_scrambler(rx_cfg_disable_scrambler),

    .ctrl_err_statistics_reset(1'b0),
    .ctrl_err_statistics_mask(7'b0),

    .cfg_frame_align_err_threshold(rx_cfg_frame_align_err_threshold),

    .status_err_statistics_cnt(rx_status_err_statistics_cnt),

    .ilas_config_valid(rx_ilas_config_valid),
    .ilas_config_addr(rx_ilas_config_addr),
    .ilas_config_data(rx_ilas_config_data),

    .status_ctrl_state(rx_status_ctrl_state),
    .status_lane_cgs_state(rx_status_lane_cgs_state),

    .status_lane_ifs_ready(rx_status_lane_ifs_ready),
    .status_lane_latency(rx_status_lane_latency),
    .status_lane_emb_state(),
    .status_lane_frame_align_err_cnt(rx_status_lane_frame_align_err_cnt)
  );

  assign cur_data_mismatch = (rx_data & rx_mask) !== ({NUM_LANES{rx_ref_data}} & rx_mask);

  always @(posedge clk) begin
    if (reset == 1'b1) begin
      data_mismatch <= 1'b0;
    end else if (rx_valid == 1'b1) begin
      if (cur_data_mismatch) begin
        data_mismatch <= 1'b1;
      end
    end
  end

  reg [NUM_LANES-1:0] lane_latency_match;

  generate for (i = 0; i < NUM_LANES; i = i + 1) begin
    wire [31:0] LANE_OFFSET = BASE_LATENCY + LANE_DELAY + BEATS_PER_MULTIFRAME + i;

    always @(posedge clk) begin
      if (rx_status_lane_ifs_ready[i] == 1'b1 &&
          rx_status_lane_latency[i*14+13:i*14+DPW_LOG2] == LANE_OFFSET) begin
        lane_latency_match[i] <= 1'b1;
      end else begin
        lane_latency_match[i] <= 1'b0;
      end
    end
  end endgenerate

  always @(*) begin
    if (rx_valid !== 1'b1 || tx_ready !== 1'b1 || data_mismatch == 1'b1 ||
        &lane_latency_match != 1'b1) begin
      failed <= 1'b1;
    end else begin
      failed <= 1'b0;
    end
  end
endmodule