405 lines
12 KiB
Coq
405 lines
12 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2015(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
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// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9684 (
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// device interface ports
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adc_clk_in_p,
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adc_clk_in_n,
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adc_data_in_p,
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adc_data_in_n,
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adc_data_or_p,
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adc_data_or_n,
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// dma interface ports
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adc_clk,
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adc_rst,
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adc_valid_0,
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adc_enable_0,
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adc_data_0,
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adc_valid_1,
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adc_enable_1,
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adc_data_1,
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adc_dovf,
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adc_dunf,
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// delay clock ports
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delay_clk,
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// axi slave interface ports
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rresp,
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s_axi_rdata,
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s_axi_rready
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);
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// parameters
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parameter ID = 0;
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parameter DEVICE_TYPE = 0;
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parameter IO_DELAY_GROUP = "dev_if_delay_group";
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parameter OR_STATUS = 1;
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// IO definitions
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input adc_clk_in_p;
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input adc_clk_in_n;
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input [13:0] adc_data_in_p;
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input [13:0] adc_data_in_n;
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input adc_data_or_p;
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input adc_data_or_n;
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output adc_clk;
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output adc_rst;
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output adc_valid_0;
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output adc_enable_0;
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output [31:0] adc_data_0;
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output adc_valid_1;
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output adc_enable_1;
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output [31:0] adc_data_1;
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input adc_dovf;
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input adc_dunf;
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input delay_clk;
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [31:0] s_axi_awaddr;
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output s_axi_awready;
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input s_axi_wvalid;
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input [31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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input s_axi_bready;
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input s_axi_arvalid;
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input [31:0] s_axi_araddr;
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output s_axi_arready;
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output s_axi_rvalid;
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output [ 1:0] s_axi_rresp;
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output [31:0] s_axi_rdata;
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input s_axi_rready;
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// internal registers
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reg up_wack = 1'b0;
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reg [31:0] up_rdata = 32'b0;
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reg up_rack = 1'b0;
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// internal clocks & resets
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wire up_clk;
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wire up_rstn;
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wire delay_rst;
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// internal signals
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wire [55:0] adc_rawdata_s;
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wire [27:0] adc_rawdata_0_s;
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wire [27:0] adc_rawdata_1_s;
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wire adc_or_0_s;
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wire adc_or_1_s;
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wire adc_status_s;
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wire adc_or_s;
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wire [14:0] up_dld_s;
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wire [74:0] up_dwdata_s;
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wire [74:0] up_drdata_s;
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wire delay_locked_s;
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wire up_status_pn_err_s;
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wire up_status_pn_oos_s;
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wire up_status_or_s;
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wire [ 1:0] up_adc_pn_err_s;
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wire [ 1:0] up_adc_pn_oos_s;
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wire [ 1:0] up_adc_or_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_s[0:3];
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wire up_rack_s[0:3];
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wire up_wack_s[0:3];
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_drp_sel_s;
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wire up_drp_wr_s;
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wire [11:0] up_drp_addr_s;
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wire [15:0] up_drp_wdata_s;
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wire [15:0] up_drp_rdata_s;
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wire up_drp_ready_s;
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wire up_drp_locked_s;
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wire mmcm_rst_s;
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//defaults
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign adc_valid = 1'b1;
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rdata <= 32'd0;
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up_rack <= 1'd0;
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up_wack <= 1'd0;
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end else begin
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up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3];
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up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3];
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up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3];
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end
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end
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// device interface instance
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axi_ad9684_if #(
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.DEVICE_TYPE(DEVICE_TYPE),
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.IO_DELAY_GROUP(IO_DELAY_GROUP),
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.OR_STATUS (OR_STATUS))
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i_ad9684_if (
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.adc_clk_in_p (adc_clk_in_p),
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.adc_clk_in_n (adc_clk_in_n),
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.adc_data_in_p (adc_data_in_p),
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.adc_data_in_n (adc_data_in_n),
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.adc_data_or_p (adc_data_or_p),
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.adc_data_or_n (adc_data_or_n),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_data_a (adc_rawdata_0_s),
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.adc_or_a (adc_or_0_s),
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.adc_data_b (adc_rawdata_1_s),
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.adc_or_b (adc_or_1_s),
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.adc_status (adc_status_s),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_dload (up_dld_s),
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.delay_wdata (up_dwdata_s),
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.delay_rdata (up_drdata_s),
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.delay_locked (delay_locked_s),
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.mmcm_rst (mmcm_rst_s),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_drp_sel (up_drp_sel_s),
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.up_drp_wr (up_drp_wr_s),
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.up_drp_addr (up_drp_addr_s),
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.up_drp_wdata (up_drp_wdata_s),
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.up_drp_rdata (up_drp_rdata_s),
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.up_drp_ready (up_drp_ready_s),
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.up_drp_locked (up_drp_locked_s));
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// common processor control instance
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assign up_status_pn_err_s = up_adc_pn_err_s[0] | up_adc_pn_err_s[1];
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assign up_status_pn_oos_s = up_adc_pn_oos_s[0] | up_adc_pn_oos_s[1];
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assign up_status_or_s = up_adc_or_s[0] | up_adc_or_s[1];
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up_adc_common #(
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.ID(ID))
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i_up_adc_common (
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.mmcm_rst (mmcm_rst_s),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_r1_mode (),
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.adc_ddr_edgesel (),
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.adc_pin_mode (),
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.adc_status (adc_status_s),
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.adc_sync_status (1'd0),
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.adc_status_ovf (adc_dovf),
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.adc_status_unf (adc_dunf),
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.adc_clk_ratio (32'b1),
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.adc_start_code (),
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.adc_sync (),
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.up_status_pn_err (up_status_pn_err_s),
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.up_status_pn_oos (up_status_pn_oos_s),
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.up_status_or (up_status_or_s),
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.up_drp_sel (up_drp_sel_s),
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.up_drp_wr (up_drp_wr_s),
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.up_drp_addr (up_drp_addr_s),
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.up_drp_wdata (up_drp_wdata_s),
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.up_drp_rdata (up_drp_rdata_s),
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.up_drp_ready (up_drp_ready_s),
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.up_drp_locked (up_drp_locked_s),
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.up_usr_chanmax (),
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.adc_usr_chanmax (8'd1),
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.up_adc_gpio_in (32'd0),
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.up_adc_gpio_out (),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[0]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[0]),
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.up_rack (up_rack_s[0]));
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// adc channel 0 instance
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axi_ad9684_channel #(
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.CHANNEL_ID (0),
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.Q_OR_I_N (0))
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i_channel_0 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_data (adc_rawdata_0_s),
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.adc_data_q (adc_rawdata_1_s),
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.adc_or (adc_or_0_s),
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.adc_dfmt_data (adc_data_0),
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.adc_valid (adc_valid_0),
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.adc_enable (adc_enable_0),
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.up_adc_pn_err (up_adc_pn_err_s[0]),
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.up_adc_pn_oos (up_adc_pn_oos_s[0]),
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.up_adc_or (up_adc_or_s[0]),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[1]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[1]),
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.up_rack (up_rack_s[1]));
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// adc channel 1 instance
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axi_ad9684_channel #(
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.CHANNEL_ID (1),
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.Q_OR_I_N (1))
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i_channel_1 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_data (adc_rawdata_1_s),
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.adc_data_q (adc_rawdata_0_s),
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.adc_or (adc_or_1_s),
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.adc_dfmt_data (adc_data_1),
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.adc_valid (adc_valid_1),
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.adc_enable (adc_enable_1),
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.up_adc_pn_err (up_adc_pn_err_s[1]),
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.up_adc_pn_oos (up_adc_pn_oos_s[1]),
|
||
|
|
.up_adc_or (up_adc_or_s[1] ),
|
||
|
|
.up_clk (up_clk),
|
||
|
|
.up_rstn (up_rstn),
|
||
|
|
.up_wreq (up_wreq_s),
|
||
|
|
.up_waddr (up_waddr_s),
|
||
|
|
.up_wdata (up_wdata_s),
|
||
|
|
.up_wack (up_wack_s[2]),
|
||
|
|
.up_rreq (up_rreq_s),
|
||
|
|
.up_raddr (up_raddr_s),
|
||
|
|
.up_rdata (up_rdata_s[2]),
|
||
|
|
.up_rack (up_rack_s[2]));
|
||
|
|
|
||
|
|
// adc delay control instance
|
||
|
|
|
||
|
|
up_delay_cntrl #(
|
||
|
|
.DATA_WIDTH(15))
|
||
|
|
i_delay_cntrl (
|
||
|
|
.delay_clk (delay_clk),
|
||
|
|
.delay_rst (delay_rst),
|
||
|
|
.delay_locked (delay_locked_s),
|
||
|
|
.up_dld (up_dld_s),
|
||
|
|
.up_dwdata (up_dwdata_s),
|
||
|
|
.up_drdata (up_drdata_s),
|
||
|
|
.up_rstn (up_rstn),
|
||
|
|
.up_clk (up_clk),
|
||
|
|
.up_wreq (up_wreq_s),
|
||
|
|
.up_waddr (up_waddr_s),
|
||
|
|
.up_wdata (up_wdata_s),
|
||
|
|
.up_wack (up_wack_s[3]),
|
||
|
|
.up_rreq (up_rreq_s),
|
||
|
|
.up_raddr (up_raddr_s),
|
||
|
|
.up_rdata (up_rdata_s[3]),
|
||
|
|
.up_rack (up_rack_s[3]));
|
||
|
|
|
||
|
|
// uP bus interface instance
|
||
|
|
|
||
|
|
up_axi i_up_axi (
|
||
|
|
.up_rstn (up_rstn),
|
||
|
|
.up_clk (up_clk),
|
||
|
|
.up_axi_awvalid (s_axi_awvalid),
|
||
|
|
.up_axi_awaddr (s_axi_awaddr),
|
||
|
|
.up_axi_awready (s_axi_awready),
|
||
|
|
.up_axi_wvalid (s_axi_wvalid),
|
||
|
|
.up_axi_wdata (s_axi_wdata),
|
||
|
|
.up_axi_wstrb (s_axi_wstrb),
|
||
|
|
.up_axi_wready (s_axi_wready),
|
||
|
|
.up_axi_bvalid (s_axi_bvalid),
|
||
|
|
.up_axi_bresp (s_axi_bresp),
|
||
|
|
.up_axi_bready (s_axi_bready),
|
||
|
|
.up_axi_arvalid (s_axi_arvalid),
|
||
|
|
.up_axi_araddr (s_axi_araddr),
|
||
|
|
.up_axi_arready (s_axi_arready),
|
||
|
|
.up_axi_rvalid (s_axi_rvalid),
|
||
|
|
.up_axi_rresp (s_axi_rresp),
|
||
|
|
.up_axi_rdata (s_axi_rdata),
|
||
|
|
.up_axi_rready (s_axi_rready),
|
||
|
|
.up_wreq (up_wreq_s),
|
||
|
|
.up_waddr (up_waddr_s),
|
||
|
|
.up_wdata (up_wdata_s),
|
||
|
|
.up_wack (up_wack),
|
||
|
|
.up_rreq (up_rreq_s),
|
||
|
|
.up_raddr (up_raddr_s),
|
||
|
|
.up_rdata (up_rdata),
|
||
|
|
.up_rack (up_rack));
|
||
|
|
|
||
|
|
endmodule
|