pluto_hdl_adi/library/util_tdd_sync/util_tdd_sync.v

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`timescale 1ns/1ps

module util_tdd_sync (
  clk,
  rstn,

  sync_en,
  sync_type,

  sync_in,
  sync_out
);

  input         clk;
  input         rstn;

  input         sync_en;
  input         sync_type;

  input         sync_in;
  output        sync_out;

  parameter TDD_SYNC_PERIOD     = 100000000;

  reg           sync_en_d1  = 1'b0;
  reg           sync_en_d2  = 1'b0;
  reg           sync_type_d1 = 1'b0;
  reg           sync_type_d2 = 1'b0;
  reg           sync_out = 1'b0;

  wire          sync_gen;

  // pulse generator

  ad_tdd_sync #(
    .TDD_SYNC_PERIOD(TDD_SYNC_PERIOD)
  )
    i_tdd_sync (
    .clk (clk),
    .rstn (rstn),
    .sync (sync_gen)
  );

  // synchronization logic

  always @(posedge clk) begin
    if(rstn == 1'b0) begin
      sync_en_d1 <= 1'b0;
      sync_en_d2 <= 1'b0;
      sync_type_d1 <= 1'b0;
      sync_type_d2 <= 1'b0;
    end else begin
      sync_en_d1 <= sync_en;
      sync_en_d2 <= sync_en_d1;
      sync_type_d1 <= sync_type;
      sync_type_d2 <= sync_type_d1;
    end
  end

  // output logic

  always @(posedge clk) begin
    if(rstn == 1'b0) begin
      sync_out <= 1'b0;
    end else begin
      if(sync_en_d2 == 1'b1) begin
        sync_out <= (sync_type_d2 == 1'b0) ? sync_gen : sync_in;
      end else begin
        sync_out <= 1'b0;
      end
    end
  end

endmodule