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pluto_hdl_adi/projects/ad469x_fmc/common/ad469x_bd.tcl

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Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
###############################################################################
spi_engine: Create interface_ip.tcl (#1251) Use tcl script instead of static xmls for the interface. Easier to maintain and are not gitignored. Rename spi_master to spi_engine because every interface should be prefixed by the IP name; in this case, spi_engine. Also, remove interface/*.sv files on make clean and git ignore them. Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2024-02-28 13:31:46 +00:00
## Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved.
Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
### SPDX short identifier: ADIBSD
###############################################################################
spi_engine: Create interface_ip.tcl (#1251) Use tcl script instead of static xmls for the interface. Easier to maintain and are not gitignored. Rename spi_master to spi_engine because every interface should be prefixed by the IP name; in this case, spi_engine. Also, remove interface/*.sv files on make clean and git ignore them. Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2024-02-28 13:31:46 +00:00
create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 ad469x_spi
ad469x: Add reference design for ad469x eval board
2020-10-08 13:10:28 +00:00
create_bd_port -dir O ad469x_spi_cnv
create_bd_port -dir I ad469x_spi_busy
source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
ad469x: Use axi_pwm_gen; clean-up Replace axi_pulse_gen with axi_pmw_gen for softare support considerations. Remove common/config.tcl and update project scripts accordingly.
2022-11-11 12:57:33 +00:00
set data_width 32
set async_spi_clk 1
set num_cs 1
set num_sdi 1
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
set num_sdo 1
ad469x: Use axi_pwm_gen; clean-up Replace axi_pulse_gen with axi_pmw_gen for softare support considerations. Remove common/config.tcl and update project scripts accordingly.
2022-11-11 12:57:33 +00:00
set sdi_delay 1
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
set echo_sclk 0
ad469x: Add reference design for ad469x eval board
2020-10-08 13:10:28 +00:00
set hier_spi_engine spi_ad469x
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
ad469x: Add reference design for ad469x eval board
2020-10-08 13:10:28 +00:00
# To support the 1MSPS (SCLK == 80 MHz), set the spi clock to 160 MHz
ad_ip_instance axi_clkgen spi_clkgen
ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5
ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8
ad_connect $sys_cpu_clk spi_clkgen/clk
ad_connect spi_clk spi_clkgen/clk_0
## to setup the sample rate of the system change the PULSE_PERIOD value
## the acutal sample rate will be PULSE_PERIOD * (1/sys_cpu_clk)
set sampling_cycle [expr int(ceil(double($spi_clk_ref_frequency * 1000000) / $adc_sampling_rate))]
ad469x: Use axi_pwm_gen; clean-up Replace axi_pulse_gen with axi_pmw_gen for softare support considerations. Remove common/config.tcl and update project scripts accordingly.
2022-11-11 12:57:33 +00:00
ad_ip_instance axi_pwm_gen ad469x_trigger_gen
ad469x: Add reference design for ad469x eval board
2020-10-08 13:10:28 +00:00
ad469x: Use axi_pwm_gen; clean-up Replace axi_pulse_gen with axi_pmw_gen for softare support considerations. Remove common/config.tcl and update project scripts accordingly.
2022-11-11 12:57:33 +00:00
ad_ip_parameter ad469x_trigger_gen CONFIG.PULSE_0_PERIOD $sampling_cycle
ad_ip_parameter ad469x_trigger_gen CONFIG.PULSE_0_WIDTH 1
ad469x: Add reference design for ad469x eval board
2020-10-08 13:10:28 +00:00
ad_connect spi_clk ad469x_trigger_gen/ext_clk
ad_connect $sys_cpu_clk ad469x_trigger_gen/s_axi_aclk
ad_connect sys_cpu_resetn ad469x_trigger_gen/s_axi_aresetn
# trigger to BUSY's negative edge
create_bd_cell -type module -reference sync_bits busy_sync
create_bd_cell -type module -reference ad_edge_detect busy_capture
set_property -dict [list CONFIG.EDGE 1] [get_bd_cells busy_capture]
ad_connect spi_clk busy_capture/clk
ad_connect busy_capture/rst GND
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_connect busy_sync/out_resetn $hier_spi_engine/${hier_spi_engine}_axi_regmap/spi_resetn
ad469x: Add reference design for ad469x eval board
2020-10-08 13:10:28 +00:00
ad_connect spi_clk busy_sync/out_clk
ad_connect busy_sync/in_bits ad469x_spi_busy
ad469x_zed: Update bd.tcl with new port names
2020-10-26 14:41:30 +00:00
ad_connect busy_sync/out_bits busy_capture/signal_in
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_connect busy_capture/signal_out $hier_spi_engine/trigger
ad469x: Add reference design for ad469x eval board
2020-10-08 13:10:28 +00:00
# dma to receive data stream
ad_ip_instance axi_dmac axi_ad469x_dma
ad_ip_parameter axi_ad469x_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_ad469x_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad469x_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad469x_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad469x_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad469x_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad469x_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad469x_dma CONFIG.DMA_DATA_WIDTH_SRC $data_width
ad_ip_parameter axi_ad469x_dma CONFIG.DMA_DATA_WIDTH_DEST 64
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_connect sys_cpu_clk $hier_spi_engine/clk
ad_connect spi_clk axi_ad469x_dma/s_axis_aclk
ad_connect sys_cpu_resetn $hier_spi_engine/resetn
ad_connect sys_cpu_resetn axi_ad469x_dma/m_dest_axi_aresetn
ad469x: Add reference design for ad469x eval board
2020-10-08 13:10:28 +00:00
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_connect spi_clk $hier_spi_engine/spi_clk
ad_connect $hier_spi_engine/m_spi ad469x_spi
ad_connect axi_ad469x_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE
ad469x: Add reference design for ad469x eval board
2020-10-08 13:10:28 +00:00
ad_ip_instance util_vector_logic cnv_gate
ad_ip_parameter cnv_gate CONFIG.C_SIZE 1
ad_ip_parameter cnv_gate CONFIG.C_OPERATION {and}
ad_connect cnv_gate/Op1 axi_ad469x_dma/s_axis_xfer_req
ad469x: Use axi_pwm_gen; clean-up Replace axi_pulse_gen with axi_pmw_gen for softare support considerations. Remove common/config.tcl and update project scripts accordingly.
2022-11-11 12:57:33 +00:00
ad_connect cnv_gate/Op2 ad469x_trigger_gen/pwm_0
ad469x: Add reference design for ad469x eval board
2020-10-08 13:10:28 +00:00
ad_connect cnv_gate/Res ad469x_spi_cnv
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
ad469x: Add reference design for ad469x eval board
2020-10-08 13:10:28 +00:00
ad_cpu_interconnect 0x44a30000 axi_ad469x_dma
ad_cpu_interconnect 0x44a70000 spi_clkgen
ad_cpu_interconnect 0x44b00000 ad469x_trigger_gen
ad_cpu_interrupt "ps-13" "mb-13" axi_ad469x_dma/irq
SPI Engine: Update spi_engine.tcl The SPI Engine cores were named directly inside the script and this would mean that for multiple SPI Engine instances IPs with the same name would appear. These updates will introduce the hierarchy name into the name given to the cores and will therefore allow for multiple instances of SPI Engine to be added to the same Xilinx project. Projects which use spi_engine.tcl will be updated to account for these changes.
2022-12-20 18:49:04 +00:00
ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq
ad469x: Add reference design for ad469x eval board
2020-10-08 13:10:28 +00:00
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_ad469x_dma/m_dest_axi