2023-07-10 08:38:46 +00:00
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###############################################################################
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## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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2023-05-09 08:15:10 +00:00
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# Primary clock definitions
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create_clock -name refclk -period 2.667 [get_ports fpga_refclk_in_p]
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# device clock
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create_clock -name rx_device_clk -period 2.667 [get_ports clkin10_p]
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# Constraint SYSREFs
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# Assumption is that REFCLK and SYSREF have similar propagation delay,
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# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
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set_input_delay -clock [get_clocks rx_device_clk] \
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[get_property PERIOD [get_clocks rx_device_clk]] \
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[get_ports {sysref2_*}]
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