2019-09-09 14:06:06 +00:00
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// ***************************************************************************
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// ***************************************************************************
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2023-07-06 13:54:40 +00:00
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// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
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2019-09-09 14:06:06 +00:00
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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2023-12-13 16:03:34 +00:00
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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2019-09-09 14:06:06 +00:00
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// clock and resets
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input sys_clk,
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input fpga_resetn,
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input hps_ref_clk,
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// hps-ddr4 (72)
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input hps_ddr_ref_clk,
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input hps_ddr_rzq,
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output [ 16:0] hps_ddr_a,
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output [ 0:0] hps_ddr_act_n,
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input [ 0:0] hps_ddr_alert_n,
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output [ 1:0] hps_ddr_ba,
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output [ 0:0] hps_ddr_bg,
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output [ 0:0] hps_ddr_ck,
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output [ 0:0] hps_ddr_ck_n,
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output [ 0:0] hps_ddr_cke,
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output [ 0:0] hps_ddr_odt,
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output [ 0:0] hps_ddr_par,
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output [ 0:0] hps_ddr_cs_n,
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output [ 0:0] hps_ddr_reset_n,
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inout [ 8:0] hps_ddr_dqs_p,
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inout [ 8:0] hps_ddr_dqs_n,
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inout [ 8:0] hps_ddr_dbi_n,
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inout [ 71:0] hps_ddr_dq,
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// hps-ethernet
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input [ 0:0] hps_emac_rx_clk,
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input [ 0:0] hps_emac_rx_ctl,
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input [ 3:0] hps_emac_rx,
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output [ 0:0] hps_emac_tx_clk,
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output [ 0:0] hps_emac_tx_ctl,
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output [ 3:0] hps_emac_tx,
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output [ 0:0] hps_emac_mdc,
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inout [ 0:0] hps_emac_mdio,
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// hps-usb
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input [ 0:0] hps_usb_clk,
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input [ 0:0] hps_usb_dir,
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input [ 0:0] hps_usb_nxt,
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output [ 0:0] hps_usb_stp,
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inout [ 7:0] hps_usb_data,
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// hps-uart
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input [ 0:0] hps_uart_rx,
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output [ 0:0] hps_uart_tx,
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// hps-i2c (shared w fmc-a, fmc-b)
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inout [ 0:0] hps_i2c_sda,
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inout [ 0:0] hps_i2c_scl,
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// fpga-gpio motherboard (led/dpsw/button)
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input [ 3:0] fpga_gpio_dpsw,
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input [ 3:0] fpga_gpio_btn,
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output [ 3:0] fpga_gpio_led,
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// sdmmc-interface
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output hps_sdmmc_clk,
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inout hps_sdmmc_cmd,
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inout [ 3:0] hps_sdmmc_data,
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// jtag-interface
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input hps_jtag_tck,
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input hps_jtag_tms,
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output hps_jtag_tdo,
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input hps_jtag_tdi,
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// hps-OOBE daughter card peripherals
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inout hps_gpio_eth_irq,
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inout hps_gpio_usb_oci,
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inout [ 1:0] hps_gpio_btn,
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inout [ 2:0] hps_gpio_led,
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// ad9213_a JESD204B high-speed interface
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input rx_ref_a_clk0,
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input rx_ref_a_clk1,
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input rx_device_clk_0,
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input [ 15:0] rx_serial_data_a,
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output rx_sync_a,
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input rx_sysref_a,
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// ad9213_b JESD204B high-speed interface
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input rx_ref_b_clk0,
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input rx_ref_b_clk1,
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input [ 15:0] rx_serial_data_b,
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output rx_sync_b,
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// configuration interfaces
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inout ad9213_dual_sdio,
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output ad9213_dual_sclk,
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output [ 1:0] ad9213_dual_csn,
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inout [ 4:0] ad9213_a_gpio,
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inout [ 4:0] ad9213_b_gpio,
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output ad9213_a_rst,
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output ad9213_b_rst,
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output ltc6952_csn,
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output ltc6946_csn,
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output ltc_sclk,
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output ltc_sdi,
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input ltc6952_sdo,
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input ltc6946_sdo,
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output adf4377_sclk,
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inout adf4377_sdio,
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output [ 1:0] adf4377_csn
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);
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// internal signals
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wire [ 63:0] gpio_i;
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wire [ 63:0] gpio_o;
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wire spi_mosi_s;
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wire spi_miso_s;
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wire ninit_done_s;
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wire h2f_reset_s;
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wire sys_resetn_s;
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wire ltc_sdo_s;
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wire adf4377_sdi_s;
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wire adf4377_sdo_s;
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wire [511:0] adc_data_0;
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wire [511:0] adc_data_1;
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wire [511:0] link_data_0;
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wire [511:0] link_data_1;
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wire [1023:0] adc_data;
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wire adc_enable_0;
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wire adc_enable_1;
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wire adc_valid;
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2022-05-04 08:15:17 +00:00
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wire [ 1:0] ltc_csn;
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wire adc_swap;
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2019-09-09 14:06:06 +00:00
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reg adc_valid_d1;
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reg [1023:0] adc_data_d1;
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reg [511:0] adc_data_0_d1;
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reg [511:0] adc_data_1_d1;
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2022-05-04 08:15:17 +00:00
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reg [511:0] adc_data_0_swap;
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reg [511:0] adc_data_1_swap;
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reg adc_swap_d1;
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reg adc_swap_d2;
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2019-09-09 14:06:06 +00:00
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// motherboard-gpio
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assign gpio_i[3:0] = fpga_gpio_dpsw;
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assign gpio_i[7:4] = fpga_gpio_btn;
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assign gpio_i[31:8] = gpio_o[31:8];
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assign fpga_gpio_led = gpio_o[11:8];
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// assignments
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2022-05-04 08:15:17 +00:00
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assign adc_swap = gpio_o[34];
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2019-09-09 14:06:06 +00:00
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assign ad9213_a_rst = gpio_o[32];
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assign ad9213_b_rst = gpio_o[33];
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assign gpio_i[63:32] = gpio_o[63:32];
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assign ltc6952_csn = ltc_csn[0];
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assign ltc6946_csn = ltc_csn[1];
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// instantiations
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ad_3w_spi #(
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2022-04-14 13:13:22 +00:00
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.NUM_OF_SLAVES(2)
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) i_ad_3w_spi_ad9213_dual (
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2019-09-09 14:06:06 +00:00
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.spi_csn (ad9213_dual_csn),
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.spi_clk (ad9213_dual_sclk),
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.spi_mosi (spi_mosi_s),
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.spi_miso (spi_miso_s),
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.spi_sdio (ad9213_dual_sdio),
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.spi_dir ());
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ad_3w_spi #(
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2022-04-14 13:13:22 +00:00
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.NUM_OF_SLAVES(2)
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) i_ad_3w_spi_adf4377 (
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2019-09-09 14:06:06 +00:00
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.spi_csn (adf4377_csn),
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.spi_clk (adf4377_sclk),
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.spi_mosi (adf4377_sdi_s),
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.spi_miso (adf4377_sdo_s),
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.spi_sdio (adf4377_sdio),
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.spi_dir ());
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// SDO line (MISO) switching for the two ltc
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assign ltc_sdo_s = (ltc_csn == 2'b10) ? ltc6952_sdo :
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(ltc_csn == 2'b01) ? ltc6946_sdo : 1'b0;
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// system reset is a combination of external reset, HPS reset and S10 init
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// done reset
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assign sys_resetn_s = fpga_resetn & ~h2f_reset_s & ~ninit_done_s;
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2022-04-14 13:13:22 +00:00
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genvar i;
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for (i = 0; i < 512; i = i + 16) begin
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2022-05-04 08:15:17 +00:00
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assign adc_data[(2*i)+31:(2*i)] ={adc_data_1_swap[i+15:i],adc_data_0_swap[i+15:i]};
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2022-04-14 13:13:22 +00:00
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end
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always @(posedge rx_device_clk_0) begin
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adc_swap_d1 <= adc_swap;
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adc_swap_d2 <= adc_swap_d1;
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if (adc_swap_d2 == 1'b0) begin
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adc_data_0_swap <= adc_data_0;
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adc_data_1_swap <= adc_data_1;
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end else begin
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adc_data_0_swap <= adc_data_1;
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adc_data_1_swap <= adc_data_0;
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end
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adc_data_0_d1 <= adc_data_0;
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adc_data_1_d1 <= adc_data_1;
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case ({adc_enable_1,adc_enable_0})
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2'b01: adc_data_d1 <= {adc_data_0,adc_data_0_d1};
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2'b10: adc_data_d1 <= {adc_data_1,adc_data_1_d1};
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2'b11: adc_data_d1 <= adc_data;
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default: adc_data_d1 <= adc_data_d1;
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endcase
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case ({adc_enable_1,adc_enable_0})
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2'b01: adc_valid_d1 <= ~adc_valid_d1;
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2'b10: adc_valid_d1 <= ~adc_valid_d1;
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2'b11: adc_valid_d1<= adc_valid;
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default: adc_valid_d1 <= adc_valid;
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endcase
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end
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2019-09-09 14:06:06 +00:00
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system_bd i_system_bd (
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.sys_clk_clk ( sys_clk ),
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.sys_rst_reset_n ( sys_resetn_s ),
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.h2f_reset_reset ( h2f_reset_s ),
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.rst_ninit_done_ninit_done ( ninit_done_s ),
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.sys_gpio_bd_in_port ( gpio_i[31: 0] ),
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.sys_gpio_bd_out_port ( gpio_o[31: 0] ),
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.sys_gpio_in_export ( gpio_i[63:32] ),
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.sys_gpio_out_export ( gpio_o[63:32] ),
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.sys_hps_io_hps_io_phery_emac0_TX_CLK ( hps_emac_tx_clk ),
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.sys_hps_io_hps_io_phery_emac0_TXD0 ( hps_emac_tx[0] ),
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.sys_hps_io_hps_io_phery_emac0_TXD1 ( hps_emac_tx[1] ),
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.sys_hps_io_hps_io_phery_emac0_TXD2 ( hps_emac_tx[2] ),
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.sys_hps_io_hps_io_phery_emac0_TXD3 ( hps_emac_tx[3] ),
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.sys_hps_io_hps_io_phery_emac0_RX_CTL ( hps_emac_rx_ctl ),
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.sys_hps_io_hps_io_phery_emac0_TX_CTL ( hps_emac_tx_ctl ),
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.sys_hps_io_hps_io_phery_emac0_RX_CLK ( hps_emac_rx_clk ),
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.sys_hps_io_hps_io_phery_emac0_RXD0 ( hps_emac_rx[0] ),
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.sys_hps_io_hps_io_phery_emac0_RXD1 ( hps_emac_rx[1] ),
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.sys_hps_io_hps_io_phery_emac0_RXD2 ( hps_emac_rx[2] ),
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.sys_hps_io_hps_io_phery_emac0_RXD3 ( hps_emac_rx[3] ),
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.sys_hps_io_hps_io_phery_emac0_MDIO ( hps_emac_mdio ),
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.sys_hps_io_hps_io_phery_emac0_MDC ( hps_emac_mdc ),
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.sys_hps_io_hps_io_phery_sdmmc_CMD ( hps_sdmmc_cmd ),
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.sys_hps_io_hps_io_phery_sdmmc_D0 ( hps_sdmmc_data[0]),
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.sys_hps_io_hps_io_phery_sdmmc_D1 ( hps_sdmmc_data[1]),
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.sys_hps_io_hps_io_phery_sdmmc_D2 ( hps_sdmmc_data[2]),
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.sys_hps_io_hps_io_phery_sdmmc_D3 ( hps_sdmmc_data[3]),
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.sys_hps_io_hps_io_phery_sdmmc_CCLK ( hps_sdmmc_clk ),
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.sys_hps_io_hps_io_phery_usb0_DATA0 ( hps_usb_data[0] ),
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.sys_hps_io_hps_io_phery_usb0_DATA1 ( hps_usb_data[1] ),
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.sys_hps_io_hps_io_phery_usb0_DATA2 ( hps_usb_data[2] ),
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.sys_hps_io_hps_io_phery_usb0_DATA3 ( hps_usb_data[3] ),
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.sys_hps_io_hps_io_phery_usb0_DATA4 ( hps_usb_data[4] ),
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.sys_hps_io_hps_io_phery_usb0_DATA5 ( hps_usb_data[5] ),
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.sys_hps_io_hps_io_phery_usb0_DATA6 ( hps_usb_data[6] ),
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.sys_hps_io_hps_io_phery_usb0_DATA7 ( hps_usb_data[7] ),
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.sys_hps_io_hps_io_phery_usb0_CLK ( hps_usb_clk ),
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.sys_hps_io_hps_io_phery_usb0_STP ( hps_usb_stp ),
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.sys_hps_io_hps_io_phery_usb0_DIR ( hps_usb_dir ),
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.sys_hps_io_hps_io_phery_usb0_NXT ( hps_usb_nxt ),
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.sys_hps_io_hps_io_phery_uart0_RX ( hps_uart_rx ),
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.sys_hps_io_hps_io_phery_uart0_TX ( hps_uart_tx ),
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.sys_hps_io_hps_io_phery_i2c1_SDA ( hps_i2c_sda ),
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.sys_hps_io_hps_io_phery_i2c1_SCL ( hps_i2c_scl ),
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.sys_hps_io_hps_io_gpio_gpio1_io0 ( hps_gpio_eth_irq ),
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.sys_hps_io_hps_io_gpio_gpio1_io1 ( hps_gpio_usb_oci ),
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.sys_hps_io_hps_io_gpio_gpio1_io4 ( hps_gpio_btn[0] ),
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.sys_hps_io_hps_io_gpio_gpio1_io5 ( hps_gpio_btn[1] ),
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.sys_hps_io_hps_io_jtag_tck ( hps_jtag_tck ),
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.sys_hps_io_hps_io_jtag_tms ( hps_jtag_tms ),
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.sys_hps_io_hps_io_jtag_tdo ( hps_jtag_tdo ),
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.sys_hps_io_hps_io_jtag_tdi ( hps_jtag_tdi ),
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.sys_hps_io_hps_io_hps_ocs_clk ( hps_ref_clk ),
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.sys_hps_io_hps_io_gpio_gpio1_io19 ( hps_gpio_led[1] ),
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.sys_hps_io_hps_io_gpio_gpio1_io20 ( hps_gpio_led[0] ),
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.sys_hps_io_hps_io_gpio_gpio1_io21 ( hps_gpio_led[2] ),
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.sys_hps_ddr_ref_clk_clk ( hps_ddr_ref_clk ),
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.sys_hps_ddr_oct_oct_rzqin ( hps_ddr_rzq ),
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.sys_hps_ddr_mem_ck ( hps_ddr_ck ),
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.sys_hps_ddr_mem_ck_n ( hps_ddr_ck_n ),
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.sys_hps_ddr_mem_a ( hps_ddr_a ),
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.sys_hps_ddr_mem_act_n ( hps_ddr_act_n ),
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.sys_hps_ddr_mem_ba ( hps_ddr_ba ),
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.sys_hps_ddr_mem_bg ( hps_ddr_bg ),
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.sys_hps_ddr_mem_cke ( hps_ddr_cke ),
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.sys_hps_ddr_mem_cs_n ( hps_ddr_cs_n ),
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.sys_hps_ddr_mem_odt ( hps_ddr_odt ),
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.sys_hps_ddr_mem_reset_n ( hps_ddr_reset_n ),
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.sys_hps_ddr_mem_par ( hps_ddr_par ),
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.sys_hps_ddr_mem_alert_n ( hps_ddr_alert_n ),
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.sys_hps_ddr_mem_dqs ( hps_ddr_dqs_p ),
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.sys_hps_ddr_mem_dqs_n ( hps_ddr_dqs_n ),
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.sys_hps_ddr_mem_dq ( hps_ddr_dq ),
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.sys_hps_ddr_mem_dbi_n ( hps_ddr_dbi_n ),
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// Link to TPL connections
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.ad9213_rx_0_link_data_data ( link_data_0 ),
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.ad9213_rx_0_link_data_valid ( link_valid_0 ),
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.ad9213_rx_1_link_data_data ( link_data_1 ),
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.ad9213_rx_1_link_data_valid ( link_valid_1 ),
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.axi_ad9213_dual_tpl_link_data_data ( {link_data_1,link_data_0} ),
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.axi_ad9213_dual_tpl_link_data_valid ( link_valid_1&link_valid_0 ),
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.axi_ad9213_dual_tpl_link_data_ready (),
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// TPL connections to PACK
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.axi_ad9213_dual_tpl_adc_ch_0_enable ( adc_enable_0 ),
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.axi_ad9213_dual_tpl_adc_ch_0_valid ( adc_valid ),
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.axi_ad9213_dual_tpl_adc_ch_0_data ( adc_data_0 ),
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.axi_ad9213_dual_tpl_adc_ch_1_enable ( adc_enable_1 ),
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.axi_ad9213_dual_tpl_adc_ch_1_valid (),
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.axi_ad9213_dual_tpl_adc_ch_1_data ( adc_data_1 ),
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// PACK to ADC FIFO
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.ad9213_adcfifo_if_adc_wr_valid ( adc_valid_d1 ),
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.ad9213_adcfifo_if_adc_wdata_data ( adc_data_d1 ),
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// SPI interface for the two ad9213
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.sys_spi_MISO ( spi_miso_s ),
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.sys_spi_MOSI ( spi_mosi_s ),
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.sys_spi_SCLK ( ad9213_dual_sclk ),
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.sys_spi_SS_n ( ad9213_dual_csn ),
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// SPI interface for the ltc
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.ltc_spi_MISO ( ltc_sdo_s ),
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.ltc_spi_MOSI ( ltc_sdi ),
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.ltc_spi_SCLK ( ltc_sclk ),
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.ltc_spi_SS_n ( ltc_csn ),
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// SPI interface for the ADF4377
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.adf4377_spi_MISO ( adf4377_sdo_s ),
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.adf4377_spi_MOSI ( adf4377_sdi_s ),
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.adf4377_spi_SCLK ( adf4377_sclk ),
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.adf4377_spi_SS_n ( adf4377_csn ),
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// JESD204B high-speed interface
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.rx_ref_clk_0_clk ( rx_ref_a_clk0 ),
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.ad9213_rx_0_serial_data_rx_serial_data ( rx_serial_data_a ),
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.rx_sysref_0_export ( rx_sysref_a ),
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.rx_sync_0_export ( rx_sync_a ),
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.rx_ref_clk_1_clk ( rx_ref_b_clk0 ),
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.ad9213_rx_1_serial_data_rx_serial_data ( rx_serial_data_b ),
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.rx_sysref_1_export ( rx_sysref_a ),
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.rx_sync_1_export ( rx_sync_b ),
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.rx_device_clk_clk ( rx_device_clk_0 ),
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// ad9213_a|b gpio
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.ad9213_dual_pio_export ( {ad9213_b_gpio, ad9213_a_gpio} ));
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endmodule
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