91 lines
5.9 KiB
Plaintext
91 lines
5.9 KiB
Plaintext
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FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
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#adrv9026
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D4 GBTCLK0_M2C_P FPGA_REF_CLK+ ref_clk_p #N/A #N/A
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D5 GBTCLK0_M2C_N FPGA_REF_CLK- ref_clk_n #N/A #N/A
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H4 CLK0_M2C_P FPGA_MMCM_CLK+ core_clk_p LVDS #N/A
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H5 CLK0_M2C_N FPGA_MMCM_CLK- core_clk_n LVDS #N/A
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A2 DP1_M2C_P SERDOUTA- rx_data_p[0] #N/A #N/A
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A3 DP1_M2C_N SERDOUTA+ rx_data_n[0] #N/A #N/A
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C6 DP0_M2C_P SERDOUTB- rx_data_p[1] #N/A #N/A
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C7 DP0_M2C_N SERDOUTB+ rx_data_n[1] #N/A #N/A
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A6 DP2_M2C_P SERDOUTC- rx_data_p[2] #N/A #N/A
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A7 DP2_M2C_N SERDOUTC+ rx_data_n[2] #N/A #N/A
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A10 DP3_M2C_P SERDOUTD- rx_data_p[3] #N/A #N/A
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A11 DP3_M2C_N SERDOUTD+ rx_data_n[3] #N/A #N/A
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A22 DP1_C2M_P SERDINC+ tx_data_p[0] #N/A #N/A
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A23 DP1_C2M_N SERDINC- tx_data_n[0] #N/A #N/A
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C2 DP0_C2M_P SERDIND- tx_data_p[1] #N/A #N/A
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C3 DP0_C2M_N SERDIND+ tx_data_n[1] #N/A #N/A
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A26 DP2_C2M_P SERDINB- tx_data_p[2] #N/A #N/A
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A27 DP2_C2M_N SERDINB+ tx_data_n[2] #N/A #N/A
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A30 DP3_C2M_P SERDINA+ tx_data_p[3] #N/A #N/A
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A31 DP3_C2M_N SERDINA- tx_data_n[3] #N/A #N/A
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G9 LA03_P SYNCIN1- rx_sync_p LVDS #N/A
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G10 LA03_N SYNCIN1+ rx_sync_n LVDS #N/A
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G36 LA33_P SYNCIN3- rx_sync_2_p LVDS #N/A
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G37 LA33_N SYNCIN3+ rx_sync_2_n LVDS #N/A
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G27 LA25_P SYNCIN2- rx_os_sync_p LVDS #N/A
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G28 LA25_N SYNCIN2+ rx_os_sync_n LVDS #N/A
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G6 LA00_CC_P FPGA_SYSREF+ sysref_p LVDS DIFF_TERM TRUE
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G7 LA00_CC_N FPGA_SYSREF- sysref_n LVDS DIFF_TERM TRUE
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H7 LA02_P SYNCOUT1+ tx_sync_p LVDS DIFF_TERM TRUE
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H8 LA02_N SYNCOUT1- tx_sync_n LVDS DIFF_TERM TRUE
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H28 LA24_P SYNCOUT2 tx_sync_1_p LVDS DIFF_TERM TRUE
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H29 LA24_N SYNCOUT2 tx_sync_1_n LVDS DIFF_TERM TRUE
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C26 LA27_P FMC_CLK_RESETB ad9528_reset_b LVCMOS18 #N/A
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C27 LA27_N FMC_SYSREF_REQUEST ad9528_sysref_req LVCMOS18 #N/A
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D11 LA05_P TEST adrv9026_test LVCMOS18 #N/A
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C10 LA06_P ORX_CTRL_A adrv9026_orx_ctrl_a LVCMOS18 #N/A
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C11 LA06_N ORX_CTRL_B adrv9026_orx_ctrl_b LVCMOS18 #N/A
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D26 LA26_P ORX_CTRL_C adrv9026_orx_ctrl_c LVCMOS18 #N/A
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C15 LA10_N ORX_CTRL_D adrv9026_orx_ctrl_d LVCMOS18 #N/A
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D18 LA13_N RX1_ENABLE adrv9026_rx1_enable LVCMOS18 #N/A
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C19 LA14_N RX2_ENABLE adrv9026_rx2_enable LVCMOS18 #N/A
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D24 LA23_N RX3_ENABLE adrv9026_rx3_enable LVCMOS18 #N/A
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D23 LA23_P RX4_ENABLE adrv9026_rx4_enable LVCMOS18 #N/A
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D17 LA13_P TX1_ENABLE adrv9026_tx1_enable LVCMOS18 #N/A
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C18 LA14_P TX2_ENABLE adrv9026_tx2_enable LVCMOS18 #N/A
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D27 LA26_N TX3_ENABLE adrv9026_tx3_enable LVCMOS18 #N/A
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C14 LA10_P TX4_ENABLE adrv9026_tx4_enable LVCMOS18 #N/A
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H11 LA04_N GPINT1 adrv9026_gpint1 LVCMOS18 #N/A
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H31 LA28_P GPINT2 adrv9026_gpint2 LVCMOS18 #N/A
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H10 LA04_P RESETB adrv9026_reset_b LVCMOS18 #N/A
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H19 LA15_P GPIO_0 adrv9026_gpio_00 LVCMOS18 #N/A
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H20 LA15_N GPIO_1 adrv9026_gpio_01 LVCMOS18 #N/A
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G18 LA16_P GPIO_2 adrv9026_gpio_02 LVCMOS18 #N/A
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G19 LA16_N GPIO_3 adrv9026_gpio_03 LVCMOS18 #N/A
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H25 LA21_P GPIO_4 adrv9026_gpio_04 LVCMOS18 #N/A
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H26 LA21_N GPIO_5 adrv9026_gpio_05 LVCMOS18 #N/A
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C22 LA18_CC_P GPIO_6 adrv9026_gpio_06 LVCMOS18 #N/A
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C23 LA18_CC_N GPIO_7 adrv9026_gpio_07 LVCMOS18 #N/A
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G25 LA22_N GPIO_8 adrv9026_gpio_08 LVCMOS18 #N/A
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H22 LA19_P GPIO_9 adrv9026_gpio_09 LVCMOS18 #N/A
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H23 LA19_N GPIO_10 adrv9026_gpio_10 LVCMOS18 #N/A
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G21 LA20_P GPIO_11 adrv9026_gpio_11 LVCMOS18 #N/A
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G22 LA20_N GPIO_12 adrv9026_gpio_12 LVCMOS18 #N/A
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G31 LA29_N GPIO_13 adrv9026_gpio_13 LVCMOS18 #N/A
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G30 LA29_P GPIO_14 adrv9026_gpio_14 LVCMOS18 #N/A
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G24 LA22_P GPIO_15_FMC adrv9026_gpio_15 LVCMOS18 #N/A
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G16 LA12_N GPIO_16 adrv9026_gpio_16 LVCMOS18 #N/A
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G15 LA12_P GPIO_17 adrv9026_gpio_17 LVCMOS18 #N/A
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D12 LA05_N GPIO_18 adrv9026_gpio_18 LVCMOS18 #N/A
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D14 LA09_P SPI_CS0 spi_csn_adrv9026 LVCMOS18 #N/A
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D15 LA09_N SPI_CS1 spi_csn_ad9528 LVCMOS18 #N/A
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H13 LA07_P SPI_CLK spi_clk LVCMOS18 #N/A
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G12 LA08_P SPI_DOUT spi_miso LVCMOS18 #N/A
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H14 LA07_N SPI_DIN spi_mosi LVCMOS18 #N/A
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