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pluto_hdl_adi/projects/common/microzed/microzed_system_bd.tcl

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Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
uzed: zed-copy
2016-01-11 18:53:22 +00:00
# create board design
# interface ports
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
create_bd_port -dir O spi0_csn_2_o
create_bd_port -dir O spi0_csn_1_o
create_bd_port -dir O spi0_csn_0_o
create_bd_port -dir I spi0_csn_i
create_bd_port -dir I spi0_clk_i
create_bd_port -dir O spi0_clk_o
create_bd_port -dir I spi0_sdo_i
create_bd_port -dir O spi0_sdo_o
create_bd_port -dir I spi0_sdi_i
create_bd_port -dir O spi1_csn_2_o
create_bd_port -dir O spi1_csn_1_o
create_bd_port -dir O spi1_csn_0_o
create_bd_port -dir I spi1_csn_i
create_bd_port -dir I spi1_clk_i
create_bd_port -dir O spi1_clk_o
create_bd_port -dir I spi1_sdo_i
create_bd_port -dir O spi1_sdo_o
create_bd_port -dir I spi1_sdi_i
create_bd_port -dir I -from 63 -to 0 gpio_i
create_bd_port -dir O -from 63 -to 0 gpio_o
create_bd_port -dir O -from 63 -to 0 gpio_t
# instance: sys_ps7
microzed: ip automatic version update
2017-04-14 14:24:24 +00:00
ad_ip_instance processing_system7 sys_ps7
common: Rename uzed to microzed Everybody calls the MicroZed microzed in their projects. Don't deviate from that to avoid potential confusion. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 19:18:09 +00:00
source $ad_hdl_dir/projects/common/microzed/microzed_system_ps7.tcl
microzed: ip automatic version update
2017-04-14 14:24:24 +00:00
ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE 0
ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1
ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 64
ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_PERIPHERAL_ENABLE 1
ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_SPI0_IO EMIO
ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 1
ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_SPI1_IO EMIO
ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0
common/microzed: Enable PS CLK1 = 200MHz
2017-09-25 12:16:58 +00:00
ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK1_PORT 1
projects/common: Add system_top _project templates Signed-off-by: laurent-19 <laurentiu.popa@analog.com> projects/common: Correct code and modify according to guidelines * Added spacing to ports declaration * Corrected coding mistakes/misspelling * Modified/added variables names * Added seetings (intel) and removed specific optimization settings * Added assignments to unassigned pins (gpios) Signed-off-by: laurent-19 <laurentiu.popa@analog.com> projects/common: Correct/Add missing wrapper ports and iobufs * Added port in wrapper (mainly spi) according to base design file * Added instances of iobufs where missing * Corrected gpio assignments or added missing ones * Corrected minor guidelines mistakes Signed-off-by: laurent-19 <laurentiu.popa@analog.com> ac701/system_top.v: Change top based on previous projects * Looked at fmcomms1, fmcomms2 from hdl_2016_r1 and datasheet Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com> projects/common: Modify templates to build without errors * Changed path for adi_env.tcl * Moved adi_project command before assign intel * Removed unnecessary spi signals * Added spi ports with default logic * a10soc: Removed pl-ddr signals and ports * ac701: system_bd: Modified mdio interface system_project: Added adi_board, adiobuf sourcing system_top: Removed hdmi, i2c, fanpwm, spdif ports according to base design * c5soc: Added version settings Removed unused gpios * microzed: system_bd: Enabled RTS1 to use FCLK system_top: Removed hdmi, i2c, unused gpios * vc709: Separated input from ouput gpio, according to bd Removed unnecessary ports Signed-off-by: laurent-19 <laurentiu.popa@analog.com> projects/common: Delete microzed vmk_es templates * Removed hp0 interconnect from cora base design * Added extra line to files de10nano Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-06-23 14:52:51 +00:00
ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST1_PORT 1
microzed: Add a secondary 200 MHz clock for PS7
2017-08-18 07:14:21 +00:00
ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0
microzed: ip automatic version update
2017-04-14 14:24:24 +00:00
ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1
ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1
ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_MODE REVERSE
common: microzed: Add clock, reset and interrupt support In order for the base project to be usable by other projects it needs to create the clock, reset and interrupt signals that are expected to exist. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 19:09:35 +00:00
microzed: ip automatic version update
2017-04-14 14:24:24 +00:00
ad_ip_instance xlconcat sys_concat_intc
ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16
common: microzed: Add clock, reset and interrupt support In order for the base project to be usable by other projects it needs to create the clock, reset and interrupt signals that are expected to exist. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 19:09:35 +00:00
microzed: ip automatic version update
2017-04-14 14:24:24 +00:00
ad_ip_instance proc_sys_reset sys_rstgen
ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
base: Add system_processor_rst for all the global clocks
2019-05-29 06:16:36 +00:00
ad_ip_instance proc_sys_reset sys_200m_rstgen
ad_ip_parameter sys_200m_rstgen CONFIG.C_EXT_RST_WIDTH 1
common: microzed: Add clock, reset and interrupt support In order for the base project to be usable by other projects it needs to create the clock, reset and interrupt signals that are expected to exist. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 19:09:35 +00:00
# system reset/clock definitions
ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0
microzed: Add a secondary 200 MHz clock for PS7
2017-08-18 07:14:21 +00:00
ad_connect sys_200m_clk sys_ps7/FCLK_CLK1
common: microzed: Add clock, reset and interrupt support In order for the base project to be usable by other projects it needs to create the clock, reset and interrupt signals that are expected to exist. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 19:09:35 +00:00
ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
base: Add system_processor_rst for all the global clocks
2019-05-29 06:16:36 +00:00
ad_connect sys_200m_reset sys_200m_rstgen/peripheral_reset
ad_connect sys_200m_resetn sys_200m_rstgen/peripheral_aresetn
ad_connect sys_200m_clk sys_200m_rstgen/slowest_sync_clk
ad_connect sys_200m_rstgen/ext_reset_in sys_ps7/FCLK_RESET1_N
uzed: zed-copy
2016-01-11 18:53:22 +00:00
common: Define three global clock nets For all the Xilinx base design, define three global clock nets, which are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk and $sys_iodelay_clk. These clock nets are connected to different clock sources depending of the FPGA architecture used on the carrier. In general the following frequencies are used: - sys_cpu_clk - 100MHz - sys_dma_clk - 200MHz or 250Mhz - sys_iodelay_clk - 200MHz or 500Mhz
2019-05-27 09:52:27 +00:00
# generic system clocks pointers
base: Add system_processor_rst for all the global clocks
2019-05-29 06:16:36 +00:00
set sys_cpu_clk [get_bd_nets sys_cpu_clk]
set sys_dma_clk [get_bd_nets sys_200m_clk]
set sys_iodelay_clk [get_bd_nets sys_200m_clk]
set sys_cpu_reset [get_bd_nets sys_cpu_reset]
set sys_cpu_resetn [get_bd_nets sys_cpu_resetn]
set sys_dma_reset [get_bd_nets sys_200m_reset]
set sys_dma_resetn [get_bd_nets sys_200m_resetn]
set sys_iodelay_reset [get_bd_nets sys_200m_reset]
set sys_iodelay_resetn [get_bd_nets sys_200m_resetn]
common: Define three global clock nets For all the Xilinx base design, define three global clock nets, which are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk and $sys_iodelay_clk. These clock nets are connected to different clock sources depending of the FPGA architecture used on the carrier. In general the following frequencies are used: - sys_cpu_clk - 100MHz - sys_dma_clk - 200MHz or 250Mhz - sys_iodelay_clk - 200MHz or 500Mhz
2019-05-27 09:52:27 +00:00
uzed: zed-copy
2016-01-11 18:53:22 +00:00
# interface connections
ad_connect ddr sys_ps7/DDR
ad_connect gpio_i sys_ps7/GPIO_I
ad_connect gpio_o sys_ps7/GPIO_O
ad_connect gpio_t sys_ps7/GPIO_T
ad_connect fixed_io sys_ps7/FIXED_IO
# spi connections
ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O
ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O
ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O
ad_connect spi0_csn_i sys_ps7/SPI0_SS_I
ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I
ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O
ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I
ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O
ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I
ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O
ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O
ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O
ad_connect spi1_csn_i sys_ps7/SPI1_SS_I
ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I
ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O
ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I
ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O
ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I
system_id: deployed ip
2019-06-28 08:41:21 +00:00
# system id
ad_ip_instance axi_sysid axi_sysid_0
ad_ip_instance sysid_rom rom_sys_0
ad_connect axi_sysid_0/rom_addr rom_sys_0/rom_addr
ad_connect axi_sysid_0/sys_rom_data rom_sys_0/rom_data
ad_connect sys_cpu_clk rom_sys_0/clk
ad_cpu_interconnect 0x45000000 axi_sysid_0
common: microzed: Add clock, reset and interrupt support In order for the base project to be usable by other projects it needs to create the clock, reset and interrupt signals that are expected to exist. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 19:09:35 +00:00
# interrupts
uzed: zed-copy
2016-01-11 18:53:22 +00:00
common: microzed: Add clock, reset and interrupt support In order for the base project to be usable by other projects it needs to create the clock, reset and interrupt signals that are expected to exist. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 19:09:35 +00:00
ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P
Remove interrupts from system_top for all xilinx projects - remove interrupts from system_top - for all suported carriers: - remove all interrupt bd pins - connect to GND all initial unconnected interrupt pins - update ad_cpu_interrupt procedure to disconnect a interrupt from GND before connectiong it to another pin.
2018-07-20 15:15:38 +00:00
ad_connect sys_concat_intc/In15 GND
ad_connect sys_concat_intc/In14 GND
ad_connect sys_concat_intc/In13 GND
ad_connect sys_concat_intc/In12 GND
ad_connect sys_concat_intc/In11 GND
ad_connect sys_concat_intc/In10 GND
ad_connect sys_concat_intc/In9 GND
ad_connect sys_concat_intc/In8 GND
ad_connect sys_concat_intc/In7 GND
ad_connect sys_concat_intc/In6 GND
ad_connect sys_concat_intc/In5 GND
ad_connect sys_concat_intc/In4 GND
ad_connect sys_concat_intc/In3 GND
ad_connect sys_concat_intc/In2 GND
ad_connect sys_concat_intc/In1 GND
ad_connect sys_concat_intc/In0 GND