2014-04-28 15:02:40 +00:00
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2014-04-30 19:07:47 +00:00
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create_clock -period "20.000 ns" -name clk_50m [get_ports {sys_clk}]
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create_clock -period "4.000 ns" -name clk_250m [get_ports {ref_clk}]
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create_clock -period "5.000 ns" -name clk_200m [get_pins {i_system_bd|sys_hps|fpga_interfaces|clocks_resets|h2f_user0_clk}]
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2014-04-28 15:02:40 +00:00
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derive_pll_clocks
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derive_clock_uncertainty
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set clk_rxlink [get_clocks {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
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2014-04-30 19:07:47 +00:00
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set_false_path -from clk_50m -to clk_200m
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set_false_path -from clk_50m -to $clk_rxlink
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set_false_path -from clk_200m -to clk_50m
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set_false_path -from clk_200m -to $clk_rxlink
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set_false_path -from $clk_rxlink -to clk_50m
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set_false_path -from $clk_rxlink -to clk_200m
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2014-04-28 15:02:40 +00:00
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