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pluto_hdl_adi/library/util_hbm/util_hbm_ooc.ttcl

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Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
util_hbm: Initial version This IP serves as storage interfacing element for external memories like HBM or DDR4 which have AXI3 or AXI4 data interfaces. The core leverages the axi_dmac as building blocks by merging an array of simplex DMA channels into duplex AXI channels. The core will split the incoming data from the source AXIS interface to multiple AXI channels, and in the read phase will merge the multiple AXI channels into a single AXIS destination interface. The number of duplex channels is set by syntheses parameter and must be set with the ratio of AXIS and AXI3/4 interface. Underflow or Overflow conditions are reported back to the data offload through the control/status interface. In case multiple AXI channels are used the source and destination AXIS interfaces widths must match.
2022-02-14 15:13:14 +00:00
<: setFileUsedIn { out_of_context synthesis implementation } :>
<: ;#Component and file information :>
<: set ComponentName [getComponentNameString] :>
<: setOutputDirectory "./" :>
<: setFileName $ComponentName :>
<: setFileExtension "_ooc.xdc" :>
# This XDC is used only for OOC mode of synthesis, implementation.
# These are default values for timing driven synthesis during OOC flow.
# These values will be overwritten during implementation with information
# from top level.
create_clock -name s_axis_aclk -period 2.5 [get_ports s_axis_aclk]
create_clock -name m_axis_aclk -period 2.5 [get_ports m_axis_aclk]
create_clock -name m_axi_aclk -period 2.5 [get_ports m_axi_aclk]