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pluto_hdl_adi/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl

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Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# dac interface
create_bd_port -dir I dac_clk_in_p
create_bd_port -dir I dac_clk_in_n
create_bd_port -dir O dac_clk_out_p
create_bd_port -dir O dac_clk_out_n
create_bd_port -dir O -from 13 -to 0 dac_data_out_a_p
create_bd_port -dir O -from 13 -to 0 dac_data_out_a_n
create_bd_port -dir O -from 13 -to 0 dac_data_out_b_p
create_bd_port -dir O -from 13 -to 0 dac_data_out_b_n
# dac peripherals
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad_ip_instance axi_ad9739a axi_ad9739a
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
Ip automatic version: Update ad*/common/ad*_bd.tcl ad6676evb/common/ad6676evb_bd.tcl ad7616_sdz/common/ad7616_bd.tcl ad7768evb/common/ad7768evb_bd.tcl ad9265_fmc/common/ad9265_bd.tcl ad9434_fmc/common/ad9434_bd.tcl ad9467_fmc/common/ad9467_bd.tcl ad9739a_fmc/common/ad9739a_fmc_bd.tcl adrv9371x/common/adrv9371x_bd.tcl adv7511/common/adv7511_bd.tcl fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 15:52:37 +00:00
ad_ip_instance axi_dmac axi_ad9739a_dma
ad_ip_parameter axi_ad9739a_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_ad9739a_dma CONFIG.DMA_TYPE_DEST 2
ad_ip_parameter axi_ad9739a_dma CONFIG.FIFO_SIZE 32
ad_ip_parameter axi_ad9739a_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9739a_dma CONFIG.CYCLIC 1
ad_ip_parameter axi_ad9739a_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad9739a_dma CONFIG.AXI_SLICE_SRC 1
ad_ip_parameter axi_ad9739a_dma CONFIG.DMA_DATA_WIDTH_DEST 256
ad_ip_parameter axi_ad9739a_dma CONFIG.DMA_DATA_WIDTH_SRC 256
ad_ip_parameter axi_ad9739a_dma CONFIG.DMA_AXI_PROTOCOL_SRC 1
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# connections (dac)
ad_connect dac_clk_in_p axi_ad9739a/dac_clk_in_p
ad_connect dac_clk_in_n axi_ad9739a/dac_clk_in_n
ad_connect dac_clk_out_p axi_ad9739a/dac_clk_out_p
ad_connect dac_clk_out_n axi_ad9739a/dac_clk_out_n
ad_connect dac_data_out_a_p axi_ad9739a/dac_data_out_a_p
ad_connect dac_data_out_a_n axi_ad9739a/dac_data_out_a_n
ad_connect dac_data_out_b_p axi_ad9739a/dac_data_out_b_p
ad_connect dac_data_out_b_n axi_ad9739a/dac_data_out_b_n
ad_connect dac_div_clk axi_ad9739a/dac_div_clk
ad_connect dac_div_clk axi_ad9739a_dma/fifo_rd_clk
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
ad_connect axi_ad9739a/dac_valid axi_ad9739a_dma/fifo_rd_en
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ad_connect axi_ad9739a/dac_ddata axi_ad9739a_dma/fifo_rd_dout
ad_connect axi_ad9739a/dac_dunf axi_ad9739a_dma/fifo_rd_underflow
# interconnect (cpu)
ad_cpu_interconnect 0x74200000 axi_ad9739a
ad_cpu_interconnect 0x7c420000 axi_ad9739a_dma
# interconnect (mem/dac)
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_dma_clk axi_ad9739a_dma/m_src_axi
ad9739a_fmc: DMA should use $sys_dma_resetn
2019-06-20 14:11:49 +00:00
ad_connect $sys_dma_resetn axi_ad9739a_dma/m_src_axi_aresetn
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# interrupts
ad_cpu_interrupt ps-12 mb-12 axi_ad9739a_dma/irq