zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/projects/adrv9009/a10gx/system_constr.sdc

13 lines
485 B
Plaintext
Raw Normal View History

adrv9009: A10GX: Initial commit
2018-10-26 10:32:18 +00:00
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
adrv9009/intel: Fix fPLL configuration When phase alignment is active, the PFD frequency value should be used as outclk1 actual frequency. The configuration interface of the fPLL does not support fractional values. If the reference clock is fractional, the tool will throw an error that requirement above is not respected. Round up the reference clock for the SERDES and the lane rate in order to overcome this issue, until it's not fixed by Intel.
2021-01-05 09:00:10 +00:00
create_clock -period "4.06504065 ns" -name ref_clk0 [get_ports {ref_clk0}]
create_clock -period "4.06504065 ns" -name ref_clk1 [get_ports {ref_clk1}]
adrv9009: A10GX: Initial commit
2018-10-26 10:32:18 +00:00
derive_pll_clocks
derive_clock_uncertainty
set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
set_false_path -from * -to [get_ports {flash_resetn}]